An enhanced redistribution layer is provided that geometrically expands redistribution layer (RDL) pads associated with a ball grid array of a wafer level package (WLP) to provide tensile stress relief during temperature cycle and/or drop testing of the WLP.

Claims

18 · 3 independent · depth 3

18 granted claims

›1.independentA wafer level package comprising:nan array of solder joint locations on a first side of the wafer level package, wherein at least one solder joint loc…+6

›2.↳ 1The wafer level package of claim 1, wherein the at least one solder joint location comprises solder joint locations proximate to each corner of the wa…d2

›3.↳ 1The wafer level package of claim 1, wherein the at least one solder joint location comprises solder joint locations about the periphery of the array o…d2+2

›6.↳ 1The wafer level package of claim 1, wherein the RDL extension wing area extends from the RDL pad area a distance of about 42 microns +/âˆ’28 microns.d2

›7.↳ 1The wafer level package of claim 1, wherein the RDL extension wing area has a width that is similar to the width of the RDL pad area +/âˆ’about 10 mic…d2

›8.independentA wafer level package comprising:na die having a first side and a second side;an array of solder joint locations on the first side of the die, the arr…+7

›9.↳ 8The wafer level package of claim 8, wherein periphery RDL pad locations, which coincide with solder joint locations about the periphery of the array, …d2+1

›11.↳ 8The wafer level package of claim 8, wherein a plurality of RDL pad locations, which coincide with various solder joint locations about the array, comp…d2+1

›13.↳ 8The wafer level package of claim 8, wherein each expanded RDL geometry comprises a width that is perpendicular to the line, the width being equal to t…d2

›14.↳ 8The wafer level package of claim 8, wherein each expanded RDL geometry comprises a length that is parallel with the line, the length being divided int…d2

›15.↳ 8The wafer level package of claim 8, wherein the array of solder joint locations is greater than or equal to an 8Ã—8 array and less than or equal to a …d2

›16.independentA silicon wafer comprising:na die being bordered on each side by streets on the wafer, the die having a first side and a second side, the die further …+2

Classifications

5 codes

IPC · International Patent Classification

Section H — Electricity

H01L23/52
H01L23/48
H01L29/40

USPC · US Patent Classification

257/784257/780

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Pendency

1.7 y

630 days filing → grant

Office actions

none on record

Responses

1 RCE

Examiner

Sheila V Clark

art unit 2823 · TC 2800

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Citations: 4 back · 0 forward

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Priority chain

1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20110108981 A1	12 May 2011

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