Inventor
Thomas Nirschl
Inventor
Essex Junction, VT, US
Overview
Patents· 68 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores46%
H10BElectronic memory devices17%
H10DInorganic electric semiconductor devices9%
H10NElectric solid-state devices not otherwise provided for9%
G06FElectric digital data processing4%
H01LSemiconductor devices2%
H03KPulse technique2%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
Y10TTechnical subjects covered by former us classification2%
PatentTitleYear
10,319,460Systems and methods utilizing a flexible read reference for a dynamic read window20199,569,354'System and method to emulate an electrically erasable programmable read-only memory'20179,389,999'System and method for emulating an EEPROM in a non-volatile memory device'20169,356,604'Integrated circuit and method for manufacturing the same'20169,343,179'Word line address scan'20169,240,225'Current sense amplifier with replica bias scheme'20169,219,063'Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor'20159,153,293'Operation scheme for non-volatile memory'20159,123,397'Circuit arrangement and method for operating a circuit arrangement'20159,070,439'Electronic device with a programmable resistive element and a method for blocking a device'20159,025,391'Circuit arrangement and method for operating a circuit arrangement'20158,743,630'Current sense amplifier with replica bias scheme'20148,670,277'Memory and method for programming memory cells'20148,670,270'Method of operating phase-change memory'20148,629,500'Integrated circuit arrangement comprising a field effect transistor, especially a tunnel field effect transistor'20148,509,007'Hybrid read scheme for multi-level data'20138,502,276'Compact memory arrays'20138,437,175'System and method for level shifter'20138,416,625'System and method for bit-line control using a driver and a pre-driver'20138,389,357'Method of fabricating a memory device having a memory array including a plurality of memory cell transistors arranged in rows and columns'20138,389,973'Memory using tunneling field effect transistors'20138,384,429'Integrated circuit and method for manufacturing same'20138,344,429'Compact memory arrays'20138,327,062'Memory circuit and method for programming in parallel a number of bits within data blocks'20128,320,189'System and method for bit-line control using a driver and a pre-driver'20128,288,813'Integrated memory device having columns having multiple bit lines'20128,243,532'NVM overlapping write method'20128,159,857'Electronic device with a programmable resistive element and a method for blocking a device'20128,130,558'System and method for level shifter'20128,125,821'Method of operating phase-change memory'20128,009,481'System and method for bit-line control'20117,995,381'Method of programming resistivity changing memory'20117,986,024'Fuse sensing scheme'20117,982,488'Phase-change memory security device'20117,974,114'Memory cell arrangements'20117,915,662'Integrated memory device having columns having multiple bit lines'20117,880,160'Memory using tunneling field effect transistors'20117,876,079'System and method for regulating a power supply'20117,864,565'Data retention monitor'20117,786,464'Integrated circuit having dielectric layer including nanocrystals'20107,778,070'Memory with dynamic redundancy configuration'20107,757,109'Circuit arrangement for activating a circuit block and method for the same'20107,692,949'Multi-bit resistive memory'20107,679,963'Integrated circuit having a drive circuit'20107,652,914'Memory including two access devices per phase change element'20107,646,625'Conditioning operations for memory cells'20107,619,917'Memory cell with trigger element'20097,606,107'Memory cell, read device for memory cell, memory assembly, and corresponding method'20097,593,255'Integrated circuit for programming a memory element'20097,582,546'Device with damaged breakdown layer'20097,580,297'Readout of multi-level storage cells'20097,577,023'Memory including write circuit for providing multiple reset pulses'20097,570,507'Quasi-differential read operation'20097,551,476'Resistive memory having shunted memory cells'20097,545,019'Integrated circuit including logic portion and memory portion'20097,541,609'Phase change memory cell having a sidewall contact'20097,531,420'Semiconductor memory cell and corresponding method of producing same'20097,515,461'Current compliant sensing architecture for multilevel phase change memory'20097,504,695'SRAM memory cell and method for compensating a leakage current flowing into the SRAM memory cell'20097,499,344'Integrated circuit memory having a read circuit'20097,474,555'Integrated circuit including resistivity changing material element'20097,436,695'Resistive memory including bipolar transistor access devices'20087,427,882'Method and apparatus for switching on a voltage supply of a semiconductor circuit and corresponding semiconductor circuit'20087,345,899'Memory having storage locations within a common volume of phase change material'20087,327,593'ROM memory cell having defined bit line voltages'20087,304,342'Semiconductor memory cell and associated fabrication method'20077,292,466'Integrated circuit having a resistive memory'20076,724,672'Integrated memory having a precharge circuit for precharging a bit line'2004Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2004–2019Patents assigned to INFINEON TECHNOLOGIES AG (53)· patent assignee history
2007–2013Based in Loiching, DE· patent location history
2008–2014Based in Essex Junction, VT, US· patent location history
2009–2016Patents assigned to NIRSCHL THOMAS (21)· patent assignee history
2009–2010Patents assigned to QIMONDA NORTH AMERICA CORP (9)· patent assignee history
2009–2015Based in Munich, DE· patent location history
2009–2012Based in München, DE· patent location history
2012–2014Patents assigned to OTTERSTEDT JAN (9)· patent assignee history
2012–2014Patents assigned to ALLERS WOLF (7)· patent assignee history
2012–2019Based in Putzbrunn, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 53 | 2004–2019 |
| NIRSCHL THOMASself | 21 | 2009–2016 |
| OTTERSTEDT JAN | 9 | 2012–2014 |
| QIMONDA NORTH AMERICA CORP | 9 | 2009–2010 |
| ALLERS WOLF | 7 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 27 | 2008–2014 |
| Putzbrunn, DE | 16 | 2012–2019 |
| Munich, DE | 13 | 2009–2015 |
| Loiching, DE | 5 | 2007–2013 |
| München, DE | 5 | 2009–2012 |