A memory device using tunneling field effect transistors (TFET) and buried bit lines is presented. The memory device includes a matrix containing rows and columns of storage cells. Each storage cell contains at least one cell transistor, which in turn contains first doped regions and second doped regions, one of which is a source and the other a drain. The memory device includes word lines, each of which is connected to storage cells of one row and bit lines, each of which is connected to storage cells of one column. The first doped regions are of a different doping type than the second doped regions.

Claims

13 · 1 independent · depth 4

13 granted claims

›1.independentA memory device comprising:na plurality of storage cells arranged in rows and columns, wherein each storage cell of the plurality of storage cells com…+12

A memory device comprising:na plurality of storage cells arranged in rows and columns, wherein each storage cell of the plurality of storage cells comprises a tunneling field effect transistorwherein each of the tunneling field effect transistors comprises a doped drain region and a doped source region,wherein the doped drain region is of a different doping type than the doped source region, each of the tunneling field effect transistors further comprises a floating gate;a first word line connected to a first row of storage cells;a first bit line to control a voltage of the doped drain regions of the tunneling field effect transistors of a first column of storage cells; anda second bit line that controls a voltage of the doped source regions of the tunneling field effect transistors of the first column of storage cells, wherein the second bit line is an electrically insulating well,wherein a first tunneling field effect transistor, of the tunneling field effect transistors, of a first storage cell has a first floating gate connected to the first word line, a first doped drain region connected to the first bit line, and a first doped source region connected to the second bit line via the electrically insulating well, the first tunneling field effect transistor having a tunneling junction and a tunneling current flowing through the tunneling junction between an inversion channel formed in an intrinsic region of a p-i-n region of the first tunneling field effect transistor and one of the first doped drain region and the first doped source region, andsaid first tunneling field effect transistor immediately adjacent a second tunneling field effect transistor, and the second tunneling field effect transistor is immediately adjacent to a third tunneling field effect transistor, andwherein a first distance between the floating gate of the first tunneling field effect transistor and the floating gate of the second tunneling field effect transistor is smaller than a second distance between the floating gate of the second tunneling field effect transistor and the floating gate of the third tunneling field effect transistor.

›2.↳ 1The device of claim 1, wherein the first bit line is a raised bit line which is raised above the first column of storage cells and the second bit line…d2+2

›5.↳ 1The device of claim 1, wherein each of the doped drain regions includes a lightly doped region and a heavily doped region, and each of the doped sourc…d2

›6.↳ 1The device of claim 1, wherein the doped drain regions and respective doped source regions are silicided.d2

›7.↳ 1The device of claim 1, wherein the first doped regions are silicided and the second doped regions are not silicided.d2

›8.↳ 1The device of claim 1, wherein the first bit line or the second bit line comprises a bit line buried below the plurality of storage cells.d2

›9.↳ 1The device of claim 1, wherein the first distance is a minimum distance between the tunneling field effect transistors in the first column of storage …d2

›10.↳ 1The memory device of claim 1 wherein, during a read operation, the inversion channel is formed in an intrinsic region of a p-i-n region of the first t…d2+2

›13.↳ 1The memory device of claim 1, further comprising a third bit line parallel to the first bit line that enables control of the voltage of doped source r…d2

Classifications

3 codes

IPC · International Patent Classification

Section H — Electricity

H01L29/788

USPC · US Patent Classification

257/315257/314

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Ori Nadav

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Type	Document	Date
related publication	US 20060033145 A1	16 Feb 2006

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