Inventor

Norman J. Rohrer

Inventor

Underhill, VT, US

Overview

1996–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 62 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique29%

G06FElectric digital data processing19%

G11CStatic stores11%

H10DInorganic electric semiconductor devices9%

G01RMeasuring electric variables8%

H02JElectric power networks4%

H10BElectronic memory devices3%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

G01KMeasuring temperature1%

PatentTitleYear

11,121,711Method for multiplexing between power supply signals for voltage limited circuits2021 10,763,859Method for multiplexing between power supply signals for voltage limited circuits2020 10,483,974Method for multiplexing between power supply signals for voltage limited circuits2019 10,437,313Processor unit efficiency control2019 10,187,045Balancing delay associated with dual-edge trigger clock gaters2019 10,084,450Method for multiplexing between power supply signals for voltage limited circuits2018 10,067,483Controlling electrical device based on temperature and voltage2018 9,712,141'Modulation of power supply voltage for varying propagation delay'2017 9,672,310'Reliability guardband compensation'2017 8,607,080'Optimizing voltage on a power plane using a host control unit to control a networked voltage regulation module array'2013 8,347,260'Method of designing an integrated circuit based on a combination of manufacturability, test coverage and, optionally, diagnostic coverage'2013 8,341,434'Optimizing voltage on a power plane using a networked voltage regulation module array'2012 8,234,554'Soft error correction in sleeping processors'2012 8,055,822'Multicore processor having storage for core-specific operational data'2011 7,996,810'System and method for designing a low leakage monotonic CMOS logic circuit'2011 7,949,971'Method and apparatus for on-the-fly minimum power state transition'2011 7,795,928'Circuit for matching semiconductor device behavior'2010 7,793,235'Method and circuit for matching semiconductor device behavior'2010 7,757,137'Method and apparatus for on-the-fly minimum power state transition'2010 7,715,222'Configurable SRAM system and method'2010 7,701,035'Laser fuse structures for high power applications'2010 7,681,153'Estimating static power consumption of integrated circuits using logic gate templates'2010 7,668,682'Method and circuit for detecting and compensating for a degradation of a semiconductor device'2010 7,642,813'Error correcting logic system'2010 7,602,635'Structure for a configurable SRAM system and method'2009 7,560,778'Charge modulation network for multiple power domains for silicon-on-insulator technology'2009 7,471,115'Error correcting logic system'2008 7,450,413'Configurable SRAM system and method'2008 7,389,478'System and method for designing a low leakage monotonic CMOS logic circuit'2008 7,382,165'Method for matching semiconductor device behavior'2008 7,352,252'Circuit and method to measure threshold voltage distributions in SRAM devices'2008 7,336,102'Error correcting logic system'2008 7,274,072'Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance'2007 7,249,358'Method and apparatus for dynamically allocating processors'2007 7,194,714'Method of reducing instantaneous current draw and an integrated circuit made thereby'2007 7,129,545'Charge modulation network for multiple power domains for silicon-on-insulator technology'2006 7,127,689'Method for preventing circuit failures due to gate oxide leakage'2006 7,084,667'Low leakage monotonic CMOS logic'2006 7,058,531'Temperature compensation in maximum frequency measurement and speed sort'2006 7,057,180'Detector for alpha particle or cosmic ray'2006 7,000,162'Integrated circuit phase partitioned power distribution for stress power reduction'2006 6,995,376'Silicon-on-insulator latch-up pulse-radiation detector'2006 6,969,859'Radiation detecting system'2005 6,954,916'Methodology for fixing Qcrit at design timing impact'2005 6,891,419'Methods and apparatus for employing feedback body control in cross-coupled inverters'2005 6,794,901'Apparatus for reducing soft errors in dynamic circuits'2004 6,613,615'Pair of FETs including a shared SOI body contact and the method of forming the FETs'2003 6,580,293'Body-contacted and double gate-contacted differential logic circuit and method of operation'2003 6,577,178'Transient gate tunneling current control'2003 6,501,294'Neuron circuit'2002 6,455,336'Power reduction method and design technique for burn-in'2002 6,433,372'Dense multi-gated device design'2002 6,433,587'SOI CMOS dynamic circuits having threshold voltage control'2002 6,344,671'Pair of FETs including a shared SOI body contact and the method of forming the FETs'2002 6,326,666'DTCMOS circuit having improved speed'2001 6,311,310'Method and apparatus for wiring integrated circuits with multiple power buses based on performance'2001 6,201,425'Method and apparatus for reducing charge sharing and the bipolar effect in stacked SOI circuits'2001 6,191,628'Circuit for controlling the slew rate of a digital signal'2001 6,097,207'Robust domino circuit design for high stress conditions'2000 5,870,404'Self-timed circuit having critical path timing detection'1999 5,867,038'Self-timed low power ratio-logic system having an input sensing circuit'1999 5,572,150'Low power pre-discharged ratio logic'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2013Patents assigned to IBM (53)· patent assignee history

1996–2013Based in Underhill, VT, US· patent location history

2012–2013Patents assigned to ROHRER NORMAN J (4)· patent assignee history

2012–2013Patents assigned to PETERSON KIRK D (3)· patent assignee history

2012–2013Patents assigned to BERNSTEIN KERRY (2)· patent assignee history

2013–2021Based in San Jose, CA, US· patent location history

2017–2021Patents assigned to APPLE INC (9)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	53	1996–2013
APPLE INC	9	2017–2021
ROHRER NORMAN Jself	4	2012–2013
PETERSON KIRK D	3	2012–2013
BERNSTEIN KERRY	2	2012–2013

Locations

Location	Patents	Span
Underhill, VT, US	52	1996–2013
San Jose, California, US	10	2013–2021