DTCMOS circuit having improved speed

The present invention relates to DTCMOS circuits which are implemented in SOI. Specifically, a circuit is described having a plurality of input transistors whose threshold voltage is controlled by an early arriving logic input signal.

Dynamic threshold metal oxide semiconductor (DTMOS) devices can be fabricated on silicon-on insulator (SOI) substrates as described, for instance in U.S. Pat. No. 5,559,368. The SOI environment has offered the promise of reducing device sizes to the submicron gate level. The MOSFET devices are fabricated using a layer of semiconductor material deposited over an insulation layer of a supporting bulk wafer. The resulting structure includes a film of monocrystalline silicon on a buried layer of silicon oxide. The bulk silicon material from which the channel of the MOSFET device is formed is either grounded, or in many applications connected to the source region of the device. In accordance with the application described in the aforesaid referenced patent, the MOSFET device monocrystalline silicon film is connected to the gate of the MOSFET device to reduce the turn-on voltage (V t ) when the gate voltage is high. The reduced threshold voltage V t for the device improves its performance in numerous respects. When the FET is OFF, the threshold voltage is increased reducing subthreshold leakage currents.

Applications which use DTCMOS devices provide not only the advantage of lower leakage currents while the MOSFET device is off, and lower threshold voltages when the device is on, but may also improve the speed of circuits utilizing MOSFET. The present invention is directed to one such application for improving the speed of DTCMOS logic circuits.

A DTCMOS circuit is implemented in SOI technology to perform a logical combination of input logic signals. The circuit includes a plurality of input transistors which receive on a gate thereof respective logic signals which are to be logically combined. The transistors formed in the SOI technology have a body contact connected to the monocrystalline silicon film of the device. Use is made of the body contact for controlling the voltage threshold V t of a device which receive a respective logic signal.

In accordance with a preferred embodiment of the invention, an earlier arriving logic signal is coupled to the gate of one input transistor, as well as to the body contact of another transistor receiving a later arriving logic signal. A data transition on the earlier arriving logic signal will lower the voltage threshold of the input transistor receiving the later arriving signal. Thus, a dynamic lowering of the voltage threshold occurs permitting an increase in speed for the logic circuit. The DTCMOS circuit provides for the usual advantages of lower voltage thresholds and reduced power supply voltage requirements, as well as improves the speed for the circuit due to the lowering of the voltage threshold on input transistors which receive later arriving logic signals.

FIG. 1 is an illustration of a DTCMOSFET implemented in SOI technology;

FIG. 2 illustrates a prior art DTCMOS inverter having gates tied to the body of each FET device;

FIG. 3 illustrates a DTCMOS NAND gate;

FIG. 4 illustrates a first embodiment of the invention which provides for a two-input NAND gate in accordance with the invention; and

FIG. 5 illustrates a three-input NAND gate in accordance with a second embodiment of the invention.

FIG. 1 illustrates a cross-section of an SOI MOSFET having a body contact connected to the silicon 14 . The DTCMOS NFET is fabricated in SOI substrates 10 having a buried oxide layer 12 formed therein with a p-silicon film 14 on the buried oxide layer 12 . An n-source region 16 is provided, as well as a drain region 18 . A gate 20 is formed over the gate insulation 22 . A body connection 19 is made between the gate 20 and body 14 permitting the body potential to be controlled in response to an applied gate voltage.

As is known from the prior art, the gate and body connection are connected together as is shown in FIGS. 2 and 3. The inverter circuit of FIG. 2 has a lower threshold voltage V t for each of the transistors 23 and 21 because the NFET 21 and PFET 23 have body contacts 22 and 24 connected to the gates of the respective device. A signal A applied to input 18 produces an inverted level represented by the voltage X at output 25 . The foregoing arrangement reduces the threshold (V t ) for each of the transistors 21 , 23 , when the FET is conducting.

The foregoing principles of the prior art are also applied in a two-input NAND gate shown in FIG. 3 . The NAND gate includes a stack of transistors 32 and 33 serially connected so that the drain and sources of each transistor are connected in series with the output 34 . Transistor 31 is a PMOS transistor in parallel with PMOS transistor 36 . The body connections for each of the transistors are connected to their respective gates. Logic signals A and B are applied to input terminals 29 and 30 , as well as to the gate of transistor 36 .

The NAND gate of FIG. 3 provides an output voltage X when input signals A and B are at a low, zero level. The circuit also has the advantage of a reduced V t for each of the transistors, thereby improving the overall circuit speed.

FIG. 4 represents a first embodiment of the invention, wherein the body potential of a transistor is controlled by the input signal of an adjacent transistor. Transistors 41 , 42 and 43 are connected in a stack, source to drain, and the stack is in turn connected across the terminals of power supply Vdd. Logic signals A and B are applied to input terminals 39 and 40 , as well as to the gate of PMOS transistor 48 . Output terminal 50 provides a signal X which is the logical combination produced by a NAND gate.

The circuit of FIG. 4 includes a transistor 42 in the stack of transistors having a body contact 45 which is connected to the gate of transistor 43 . The aforesaid connection permits the body of transistor 42 to be set at a high potential when logic signal B goes high. In this way, if logic signal B arrives ahead of logic signal A, the threshold V t of transistor 42 will have been lowered and transistor 42 will otherwise turn on sooner than had body contact 45 been connected to its gate. Accordingly, with the foregoing arrangement, when logic signal B is low, a higher threshold voltage is maintained on transistor 42 providing enhanced noise immunity, and reduced leakage currents. However, when the logic signal B goes to a high value, the threshold voltage for transistor 42 will be lowered.

The same principle may be applied to the three-input NAND gate shown in FIG. 5 . Input terminals 51 , 52 and 53 receive logic signals A, B and C. Additionally, PMOS transistors 60 and 61 receive logic signals B and C as well. An output terminal 62 provides the logical output of the NAND function for input signals A, B and C.

As is illustrated in FIG. 5, the body contact of transistors 56 , 57 and 58 is connected to the input terminal 53 . Each of these NFET devices when receiving a logic signal C provide a lower threshold voltage for the respective transistors 56 , 57 and 58 . Thus, if signals A and B arrive later than signal C, the threshold values for transistors 56 and 57 have already been reduced, effectively speeding up the generation of an output signal on terminal 62 . The lower voltage thresholds on each of the transistors means also that the power supply voltage Vdd may be correspondingly reduced as is beneficial in DTCMOS circuitry.

The foregoing description of the invention illustrates and describes the present invention. Additionally, the disclosure shows and describes only the preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is capable of use in various other combinations, modifications, and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein, commensurate with the above teachings, and/or the skill or knowledge of the relevant art. The embodiments described hereinabove are further intended to explain best modes known of practicing the invention and to enable others skilled in the art to utilize the invention in such, or other, embodiments such as for NOR gates, AND gates, tribuffers, etc., and with the various modifications required by the particular applications or uses of the invention. Accordingly, the description is not intended to limit the invention to the form disclosed herein. Also, it is intended that the appended claims be construed to include alternative embodiments.