Inventor
Morihisa Hirata
Inventor
Kanagawa, JP
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices33%
G06FElectric digital data processing19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%
D06MTreatment, not provided for elsewhere in class d06, of fibres, threads, yarns, fabrics, feathers or fibrous goods made from such materials8%
D10BIndexing scheme associated with sublasses of section d, relating to textiles8%
H03KPulse technique6%
G01RMeasuring electric variables2%
G11CStatic stores2%
H02HEmergency protective circuit arrangements2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
PatentTitleYear
8,749,932'Semiconductor device with a plurality of power supply systems'20148,270,132'Semiconductor device with a plurality of power supply systems'20128,230,373'ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device'20128,008,727'Semiconductor integrated circuit device including a pad and first mosfet'20117,986,156'Semiconductor device including address signal generating protion and digital-to-analog converter'20117,869,174'Semiconductor device with a plurality of power supply systems'20117,853,909'ESD analysis device and ESD analysis program used for designing semiconductor device and method of designing semiconductor device'20107,631,279'Semiconductor integrated device and apparatus for designing the same'20097,624,365'Semiconductor integrated device and apparatus for designing the same'20097,552,404'Semiconductor integrated device and apparatus for designing the same'20097,312,517'System-in-package type semiconductor device'20077,196,377'MOS type semiconductor device having electrostatic discharge protection arrangement'20077,076,757'Semiconductor integrated device and apparatus for designing the same'20066,975,979'Method and computer software product for calculating and presenting a numerical value representative of a property of a circuit'20056,670,679'Semiconductor device having an ESD protective circuit'20036,629,295'Design automation method and device'20036,600,210'Semiconductor device and method of manufacturing the same'20036,469,354'Semiconductor device having a protective circuit'20026,351,012'Semiconductor device having a protective circuit'20026,321,364'Method for designing integrated circuit device based on maximum load capacity'20016,191,454'Protective resistance element for a semiconductor device'20015,905,287'Semiconductor device with high voltage protection'19995,449,940'Semiconductor integrated circuit having improved protection element'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2003Patents assigned to NEC CORP (6)· patent assignee history
1995–2005Based in Tokyo, JP· patent location history
2003–2009Patents assigned to NEC ELECTRONICS CORP (9)· patent assignee history
2006–2014Based in Kanagawa, JP· patent location history
2010–2014Patents assigned to RENESAS ELECTRONICS CORP (7)· patent assignee history
2012–2014Patents assigned to HIRATA MORIHISA (3)· patent assignee history
2012–2014Patents assigned to OKAMOTO HITOSHI (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| NEC ELECTRONICS CORP | 9 | 2003–2009 |
| RENESAS ELECTRONICS CORP | 7 | 2010–2014 |
| NEC CORP | 6 | 1995–2003 |
| HIRATA MORIHISAself | 3 | 2012–2014 |
| OKAMOTO HITOSHI | 2 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Kanagawa, JP | 13 | 2006–2014 |
| Tokyo, JP | 10 | 1995–2005 |