Inventor

Cyprian Emeka Uzoh

Inventor

San Jose, CA, US

Overview

1998–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 330 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Wprimary

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%

H01LSemiconductor devices19%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1016%

C25DProcesses for the electrolytic or electrophoretic production of coatings8%

Y10TTechnical subjects covered by former us classification5%

H05KPrinted circuits4%

C25FProcesses for the electrolytic removal of materials from objects4%

H10DInorganic electric semiconductor devices3%

B24BMachines, devices, or processes for grinding or polishing3%

B23HWorking of metal by the action of a high concentration of electric current on a workpiece using an electrode which takes the place of a tool2%

PatentTitleYear

11,088,099Multi-metal contact structure in microelectronic component2021 11,056,390Structures and methods for reliable packages2021 11,037,919Techniques for processing devices2021 11,031,285Diffusion barrier collar for interconnects2021 11,011,494Layer structures for making direct metal-to-metal bonds at low temperatures in microelectronics2021 11,004,757Bonded structures2021 10,985,133Die processing2021 10,957,661Interconnections for a substrate associated with a backside reveal2021 10,910,344Systems and methods for releveled bump planes for chiplets2021 10,896,902Systems and methods for efficient transfer of semiconductor elements2021 10,892,246Structures and methods for low temperature bonding using nanoparticles2021 10,886,250Structures and methods for low temperature bonding using nanoparticles2021 10,879,212Processed stacked dies2020 10,879,226Stacked dies and methods for forming bonded structures2020 10,849,240Contact structures with porous networks for solder connections, and methods of fabricating same2020 10,840,205Chemical mechanical polishing for hybrid bonding2020 10,840,135Flat metal features for microelectronics applications2020 10,818,629Tall and fine pitch interconnects2020 10,813,214Cavities containing multi-wiring structures and devices2020 10,804,151Systems and methods for producing flat surfaces in interconnect structures2020 10,796,936Die tray with channels2020 10,790,262Low temperature bonded structures2020 10,727,219Techniques for processing devices2020 10,714,449Die processing2020 10,707,087Processing stacked substrates2020 10,700,002Ultra high performance interposer2020 10,672,654Microelectronic assembly from processed substrate2020 10,629,567Multiple plated via arrays of different wire heights on same substrate2020 10,629,577Direct-bonded LED arrays and applications2020 10,586,759Interconnection substrates for interconnection between circuit modules, and methods of manufacture2020 10,586,785Embedded graphite heat spreader for 3DIC2020 10,535,564Structures and methods for reliable packages2020 10,535,626Structures and methods for low temperature bonding using nanoparticles2020 10,531,574Contact structures with porous networks for solder connections, and methods of fabricating same2020 10,522,457Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates2019 10,515,925Die processing2019 10,515,838Method and apparatus for stacking devices in an integrated circuit assembly2019 10,515,913Multi-metal contact structure2019 10,508,030Seal for microelectronic assembly2019 10,475,726Low CTE component with wire bond interconnects2019 10,475,733Method and structures for heat dissipating interposers2019 10,446,532Systems and methods for efficient transfer of semiconductor elements2019 10,446,441Flat metal features for microelectronics applications2019 10,440,822Interposers with electrically conductive features having different porosities2019 10,418,338Interconnections for a substrate associated with a backside reveal2019 10,410,977High performance compliant substrate2019 10,396,114Method of fabricating low CTE interposer without TSV structure2019 10,333,014Method and substrates for making photovoltaic cells2019 10,332,854Anchoring structure of fine pitch bva2019 10,332,833Ultra high performance interposer2019 10,325,880Hybrid 3D/2.5D interposer2019 10,297,582BVA interposer2019 10,290,613Multiple bond via arrays of different wire heights on a same substrate2019 10,283,449Low stress vias2019 10,283,484Low cost substrates2019 10,269,756Die processing2019 10,211,160Microelectronic assembly with redistribution structure formed on carrier2019 10,204,893Stacked dies and methods for forming bonded structures2019 10,199,275Systems and methods for producing flat surfaces in interconnect structures2019 10,181,411Method for fabricating a carrier-less silicon interposer2019 10,177,114Hybrid 3D/2.5D interposer2019 10,177,086Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates2019 10,163,757Method and structures for via substrate repair and assembly2018 10,163,675Method and apparatus for stacking devices in an integrated circuit assembly2018 10,159,148Porous alumina templates for electronic packages2018 10,147,548Capacitors using porous alumina structures2018 10,103,093Via structure for signal equalization2018 10,103,121Tall and fine pitch interconnects2018 10,103,094Method and structures for heat dissipating interposers2018 10,090,231Conductive connections, structures with such connections, and methods of manufacture2018 10,049,998Conductive connections, structures with such connections, and methods of manufacture2018 10,037,940Reliable packaging and interconnect structures2018 10,032,715Ultra high performance interposer2018 10,032,647Low CTE component with wire bond interconnects2018 10,026,717Multiple bond via arrays of different wire heights on a same substrate2018 10,015,881Cavities containing multi-wiring structures and devices2018 10,014,243Interconnection substrates for interconnection between circuit modules, and methods of manufacture2018 10,008,534Microelectronic package with horizontal and vertical interconnections2018 9,991,231Stacked die integrated circuit2018 9,953,957Embedded graphite heat spreader for 3DIC2018 9,947,618Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates2018 9,905,537'Compact semiconductor package and related methods'2018 9,905,713'Method and substrates for material application'2018 9,893,030'Reliable device assembly'2018 9,888,584'Contact structures with porous networks for solder connections, and methods of fabricating same'2018 9,877,487'Compositions for effective fly population suppression'2018 9,871,019'Flipped die stack assemblies with leadframe interconnects'2018 9,865,548'Polymer member based interconnect'2018 9,865,675'Making multilayer 3D capacitors using arrays of upstanding rods or ridges'2018 9,859,234'Methods and structures to repair device warpage'2018 9,852,969Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects2017 9,853,000Warpage reduction in structures with electrical circuitry2017 9,853,004Interconnections for a substrate associated with a backside reveal2017 9,842,819'Tall and fine pitch interconnects'2017 9,824,974'Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies'2017 9,818,713'Structures and methods for low temperature bonding using nanoparticles'2017 9,812,360'Systems and methods for producing flat surfaces in interconnect structures'2017 9,799,626'Semiconductor packages and other circuit modules with porous and non-porous stabilizing layers'2017 9,793,198'Conductive connections, structures with such connections, and methods of manufacture'2017 9,780,042'Tunable composite interposer'2017 9,769,923'Interposers'2017 9,761,517'Porous alumina templates for electronic packages'2017 9,754,866'Reversed build-up substrate for 2.5D'2017 9,741,620'Structures and methods for reliable packages'2017 9,741,696'Thermal vias disposed in a substrate proximate to a well thereof'2017 9,728,527'Multiple bond via arrays of different wire heights on a same substrate'2017 9,711,401'Reliable packaging and interconnect structures'2017 9,691,702'Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates'2017 9,685,420'Localized sealing of interconnect structures in small gaps'2017 9,685,401'Structures for heat dissipating interposers'2017 9,673,124'Device and method for localized underfill'2017 9,666,514'High performance compliant substrate'2017 9,666,521'Ultra high performance interposer'2017 9,659,858'Low-stress vias'2017 9,646,917'Low CTE component with wire bond interconnects'2017 9,634,412'Connector structures and methods'2017 9,633,971'Structures and methods for low temperature bonding using nanoparticles'2017 9,615,451'Porous alumina templates for electronic packages'2017 9,607,928'Method and structures for via substrate repair and assembly'2017 9,601,398'Thin wafer handling and known good die test method'2017 9,601,467'Microelectronic package with horizontal and vertical interconnections'2017 9,583,456'Multiple bond via arrays of different wire heights on a same substrate'2017 9,583,417'Via structure for signal equalization'2017 9,583,426'Multi-layer substrates suitable for interconnection between circuit modules'2017 9,570,385'Method for fabrication of interconnection circuitry with electrically conductive features passing through a support and comprising core portions formed using nanoparticle-containing inks'2017 9,560,773'Electrical barrier layers'2017 9,558,964'Method of fabricating low CTE interposer without TSV structure'2017 9,558,998'Systems and methods for producing flat surfaces in interconnect structures'2017 9,551,083'Paddle for materials processing'2017 9,548,273'Integrated circuit assemblies with rigid layers used for protection against mechanical thinning and for other purposes, and methods of fabricating such assemblies'2017 9,524,943'Compact semiconductor package and related methods'2016 9,502,390'BVA interposer'2016 9,496,154'Use of underfill tape in microelectronic components, and microelectronic components with cavities coupled to through-substrate vias'2016 9,484,325'Interconnections for a substrate associated with a backside reveal'2016 9,455,237'Bowl-shaped solder structure'2016 9,455,162'Low cost interposer and method of fabrication'2016 9,455,181'Vias in porous substrates'2016 9,443,837'Z-connection for a microelectronic package using electroless plating'2016 9,437,536'Reversed build-up substrate for 2.5D'2016 9,437,566'Conductive connections, structures with such connections, and methods of manufacture'2016 9,437,557'High density three-dimensional integrated capacitors'2016 9,433,093'High strength through-substrate vias'2016 9,418,879'Low cost interposer and method of fabrication'2016 9,418,924'Stacked die integrated circuit'2016 9,412,646'Via in substrate with deposited layer'2016 9,412,806'Making multilayer 3D capacitors using arrays of upstanding rods or ridges'2016 9,398,700'Method of forming a reliable microelectronic assembly'2016 9,397,051'Warpage reduction in structures with electrical circuitry'2016 9,397,038'Microelectronic components with features wrapping around protrusions of conductive vias protruding from through-holes passing through substrates'2016 9,385,036'Reliable packaging and interconnect structures'2016 9,379,008'Metal PVD-free conducting structures'2016 9,379,074'Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects'2016 9,373,585'Polymer member based interconnect'2016 9,365,947'Method for preparing low cost substrates'2016 9,368,479'Thermal vias disposed in a substrate proximate to a well thereof'2016 9,362,204'Tunable composite interposer'2016 9,355,905'Methods and structure for carrier-less thin wafer handling'2016 9,349,614'Device and method for localized underfill'2016 9,349,669'Reduced stress TSV and interposer structures'2016 9,331,043'Localized sealing of interconnect structures in small gaps'2016 9,323,010'Structures formed using monocrystalline silicon and/or other materials for optical and other applications'2016 9,318,385'Systems and methods for producing flat surfaces in interconnect structures'2016 9,287,164'Single exposure in multi-damascene process'2016 9,263,394'Multiple bond via arrays of different wire heights on a same substrate'2016 9,257,396'Compact semiconductor package and related methods'2016 9,245,670'Reliable wire method'2016 9,237,648'Carrier-less silicon interposer'2016 9,226,396'Porous alumina templates for electronic packages'2015 9,214,425'Low-stress vias'2015 9,190,463'High density three-dimensional integrated capacitors'2015 9,184,323'Method and substrates for making photovoltaic cells'2015 9,142,508'Single exposure in multi-damascene process'2015 9,123,780'Method and structures for heat dissipating interposers'2015 9,125,333'Electrical barrier layers'2015 9,123,703'Systems and methods for producing flat surfaces in interconnect structures'2015 9,076,594'Capacitors using porous alumina structures'2015 9,076,785'Method and structures for via substrate repair and assembly'2015 9,070,676'Bowl-shaped solder structure'2015 9,064,933'Methods and structure for carrier-less thin wafer handling'2015 9,030,017'Z-connection using electroless plating'2015 9,024,205'Advanced device assembly structures and methods'2015 9,000,600'Reduced stress TSV and interposer structures'2015 8,981,564'Metal PVD-free conducting structures'2015 8,978,247'TSV fabrication using a removable handling structure'2015 8,975,751'Vias in porous substrates'2015 8,963,335'Tunable composite interposer'2015 8,946,899'Via in substrate with deposited layer'2015 8,916,781'Cavities containing multi-wiring structures and devices'2014 8,884,427'Low CTE interposer without TSV structure'2014 8,846,447'Thin wafer handling and known good die test method'2014 8,829,680'Reliable packaging and interconnect structures'2014 8,816,505'Low stress vias'2014 8,785,790'High strength through-substrate vias'2014 8,772,946'Reduced stress TSV and interposer structures'2014 8,757,897'Optical interposer'2014 8,742,541'High density three-dimensional integrated capacitors'2014 8,728,934'Systems and methods for producing flat surfaces in interconnect structures'2014 8,692,118'Reliable wire structure and method'2014 8,609,540'Reliable packaging and interconnect structures'2013 8,076,237'Method and apparatus for 3D interconnect'2011 7,704,880'Method of forming contact layers on substrates'2010 7,670,473'Workpiece surface influencing device designs for electrochemical mechanical processing and method of using the same'2010 RE040983'Method to plate C4 to copper stud'2009 7,572,354'Electrochemical processing of conductive surface'2009 7,503,830'Apparatus for reduction of defects in wet processed layers'2009 7,491,308'Method of making rolling electrical contact to wafer front surface'2009 7,476,304'Apparatus for processing surface of workpiece with small electrodes and surface contacts'2009 7,456,501'Semiconductor structure having recess with conductive metal'2008 7,416,975'Method of forming contact layers on substrates'2008 7,378,004'Pad designs and structures for a versatile materials processing apparatus'2008 7,329,335'Device providing electrical contact to the surface of a semiconductor workpiece during processing'2008 7,311,811'Device providing electrical contact to the surface of a semiconductor workpiece during processing'2007 7,309,406'Method and apparatus for plating and polishing semiconductor substrate'2007 7,309,413'Providing electrical contact to the surface of a semiconductor workpiece during processing'2007 7,282,124'Device providing electrical contact to the surface of a semiconductor workpiece during processing'2007 7,250,104'Method and system for optically enhanced metal planarization'2007 7,244,347'Method and system to provide electrical contacts for electrotreating processes'2007 7,238,092'Low-force electrochemical mechanical processing method and apparatus'2007 7,211,174'Method and system to provide electrical contacts for electrotreating processes'2007 7,204,917'Workpiece surface influencing device designs for electrochemical mechanical processing and method of using the same'2007 7,201,829'Mask plate design'2007 7,195,696'Electrode assembly for electrochemical processing of workpiece'2007 7,195,700'Method of electroplating copper layers with flat topography'2007 7,189,146'Method for reduction of defects in wet processed layers'2007 7,147,766'Chip interconnect and packaging deposition methods and structures'2006 7,122,473'Edge and bevel cleaning process and system'2006 7,115,510'Method for electrochemically processing a workpiece'2006 7,097,755'Electrochemical mechanical processing with advancible sweeper'2006 6,979,393'Method for plating copper conductors and devices formed'2005 6,974,769'Conductive structure fabrication process using novel layered structure and conductive structure fabricated thereby for use in multi-level metallization'2005 6,969,456'Method of using vertically configured chamber used for multiple processes'2005 6,946,066'Multi step electrodeposition process for reducing defects and minimizing film thickness'2005 6,946,716'Electroplated interconnection structures on integrated circuit chips'2005 6,943,112'Defect-free thin and planar film processing'2005 6,942,780'Method and apparatus for processing a substrate with minimal edge exclusion'2005 6,936,154'Planarity detection methods and apparatus for electrochemical mechanical processing systems'2005 6,932,896'Method and apparatus for avoiding particle accumulation in electrodeposition'2005 6,905,588'Packaging deposition methods'2005 6,884,334'Vertically configured chamber used for multiple processes'2005 6,866,763'Method and system monitoring and controlling film thickness profile during plating and electroetching'2005 6,867,136'Method for electrochemically processing a workpiece'2005 6,861,354'Method and structure to reduce defects in integrated circuits and substrates'2005 6,852,208'Method and apparatus for full surface electrotreating of a wafer'2005 6,852,630'Electroetching process and system'2005 6,837,979'Method and apparatus for depositing and controlling the texture of a thin film'2005 6,821,409'Electroetching methods and systems using chemical and mechanical influence'2004 6,815,354'Method and structure for thru-mask contact electrodeposition'2004 6,797,132'Apparatus for plating and polishing a semiconductor workpiece'2004 6,780,772'Method and system to provide electroplanarization of a workpiece with a conducting material layer'2004 6,777,338'Edge and bevel cleaning process and system'2004 6,773,576'Anode assembly for plating and planarizing a conductive layer'2004 6,768,203'Open-bottomed via liner structure and method for fabricating same'2004 6,716,084'Carrier head for holding a wafer and allowing processing on a front face thereof to occur'2004 6,709,562'Method of making electroplated interconnection structures on integrated circuit chips'2004 6,695,962'Anode designs for planar metal deposits with enhanced electrolyte solution blending and process of supplying electrolyte solution using such designs'2004 6,692,588'Method and apparatus for simultaneously cleaning and annealing a workpiece'2004 6,685,814'Method for enhancing the uniformity of electrodeposition or electroetching'2004 6,666,959'Semiconductor workpiece proximity plating methods and apparatus'2003 6,649,523'Method and system to provide material removal and planarization employing a reactive pad'2003 6,630,059'Workpeice proximity plating apparatus'2003 6,612,915'Work piece carrier head for plating and polishing'2003 6,610,190'Method and apparatus for electrodeposition of uniform film with minimal edge exclusion on substrate'2003 6,600,230'Seedlayer for plating metal in deep submicron structures'2003 6,582,579'Methods for repairing defects on a semiconductor substrate'2003 6,572,982'Electromigration-resistant copper microstructure'2003 6,569,783'Graded composition diffusion barriers for chip wiring applications'2003 6,497,800'Device providing electrical contact to the surface of a semiconductor workpiece during metal plating'2002 6,492,262'Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies'2002 6,482,307'Method of and apparatus for making electrical contact to wafer surface for full-face electroplating or electropolishing'2002 6,478,936'Anode assembly for plating and planarizing a conductive layer'2002 6,465,376'Method and structure for improving electromigration of chip interconnects'2002 6,437,440'Thin film metal barrier for electrical interconnections'2002 6,429,519'Wiring structures containing interconnected metal and wiring levels including a continuous, single crystalline or polycrystalline conductive material having one or more twin boundaries'2002 6,413,403'Method and apparatus employing pad designs and structures with improved fluid distribution'2002 6,413,388'Pad designs and structures for a versatile materials processing apparatus'2002 6,413,854'Method to build multi level structure'2002 6,409,904'Method and apparatus for depositing and controlling the texture of a thin film'2002 6,406,608'Apparatus to monitor and add plating solution to plating baths and controlling quality of deposited metal'2002 6,399,496'Copper interconnection structure incorporating a metal seed layer'2002 6,380,628'Microstructure liner having improved adhesion'2002 6,372,081'Process to prevent copper contamination of semiconductor fabs'2002 6,354,916'Modified plating solution for plating and planarization and process utilizing same'2002 6,355,153'Chip interconnect and packaging deposition methods and structures'2002 6,352,623'Vertically configured chamber used for multiple processes'2002 6,344,129'Method for plating copper conductors and devices formed'2002 6,339,258'Low resistivity tantalum'2002 6,337,151'Graded composition diffusion barriers for chip wiring applications'2002 6,337,218'Method to test devices on high performance ULSI wafers'2002 6,333,560'Process and structure for an interlock and high performance multilevel structures for chip interconnects and packaging technologies'2001 6,333,120'Method for controlling the texture and microstructure of plated copper and plated structure'2001 6,331,237'Method of improving contact reliability for electroplating'2001 6,328,872'Method and apparatus for plating and polishing a semiconductor substrate'2001 6,297,140'Method to plate C4 to copper stud'2001 6,291,885'Thin metal barrier for electrical interconnections'2001 6,274,935'Copper wire-bonding pad'2001 6,270,646'Electroplating apparatus and method using a compressible contact'2001 6,261,426'Method and apparatus for enhancing the uniformity of electrodeposition or electroetching'2001 6,258,707'Triple damascence tungsten-copper interconnect structure'2001 6,258,717'Method to produce high quality metal fill in deep submicron vias and lines'2001 6,251,528'Method to plate C4 to copper stud'2001

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2009Patents assigned to IBM (64)· patent assignee history

1998–2008Based in Hopewell Junction, NY, US· patent location history

2000–2003Based in Beacon, NY, US· patent location history

2001–2005Patents assigned to NUTOOL INC (26)· patent assignee history

2001–2009Based in Milpitas, CA, US· patent location history

2002Based in Dutchess County, NY, US· patent location history

2004–2021Based in San Jose, CA, US· patent location history

2013–2020Patents assigned to TESSERA INC (28)· patent assignee history

2014–2021Patents assigned to INVENSAS CORP (144)· patent assignee history

2019–2021Patents assigned to INVENSAS BONDING TECH INC (22)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INVENSAS CORP	144	2014–2021
IBM	64	1998–2009
TESSERA INC	28	2013–2020
NUTOOL INC	26	2001–2005
INVENSAS BONDING TECH INC	22	2019–2021

Locations

Location	Patents	Span
San Jose, California, US	222	2004–2021
Milpitas, California, US	60	2001–2009
Hopewell Junction, New York, US	43	1998–2008
Beacon, New York, US	4	2000–2003
Dutchess County, New York, US	1	2002