Inventor

Ravi Pillarisetty

Inventor

Portland, OR, US

Overview

2009–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 285 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices27%

H01LSemiconductor devices23%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

B82YSpecific uses or applications of nanostructures10%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%

H10NElectric solid-state devices not otherwise provided for5%

H10BElectronic memory devices4%

G06NComputing arrangements based on specific computational models2%

G11CStatic stores2%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%

PatentTitleYear

11,114,471Thin film transistors having relatively increased width and shared bitlines2021 11,114,530Quantum well stacks for quantum dot devices2021 11,107,891Hexagonal arrays for quantum dot devices2021 11,101,376Non-planar transition metal dichalcogenide devices2021 11,101,270Techniques and mechanisms for operation of stacked transistors2021 11,101,352Quantum dot array devices with shared gates2021 11,101,377Transistor device with heterogeneous channel structure bodies and method of providing same2021 11,088,204Three terminal selectors for memory applications and their methods of fabrication2021 11,081,483CMOS circuit with a group III-nitride transistor and method of providing same2021 11,075,293Qubit-detector die assemblies2021 11,075,207SRAM using 2T-2S2021 11,063,040Quantum dot devices2021 11,031,072Dynamic random access memory including threshold switch2021 11,011,550Self-aligned top-gated non-planar oxide semiconductor thin film transistors2021 11,011,693Integrated quantum circuit assemblies for cooling apparatus2021 11,004,982Gate for a transistor2021 10,991,802Quantum dot devices with gate interface materials2021 10,978,582Gate patterning for quantum dot devices2021 10,964,820Vertical transistor devices and techniques2021 10,950,733Deep gate-all-around semiconductor device having germanium or group III-V active layer2021 10,930,500Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices2021 10,930,679Thin film transistors with a crystalline oxide semiconductor source/drain2021 10,910,556Magnetic and spin logic devices based on Jahn-Teller materials2021 10,910,488Quantum dot devices with fins and partially wrapped gates2021 10,910,436Asymmetric selectors for memory cells2021 10,897,009Resistive memory cells and precursors thereof, methods of making the same, and devices including the same2021 10,879,446Vertical flux bias lines coupled to vertical squid loops in superconducting qubits2020 10,872,660Resistive memory devices with transition metal dichalcogenide (TMD) materials as ballast resistors to control current flow through the devices2020 10,850,977Group III-N MEMS structures on a group IV substrate2020 10,847,705Reducing crosstalk from flux bias lines in qubit devices2020 10,840,431Multilayer selector device with low holding voltage2020 10,825,861Multilayer selector device with low leakage current2020 10,818,799Vertical transistor devices and techniques2020 10,811,461Access transmission gate2020 10,811,336Temperature management of electronic circuitry of electronic devices, memory devices, and computing devices2020 10,804,399Double-sided quantum dot devices2020 10,803,396Quantum circuit assemblies with Josephson junctions utilizing resistive switching materials2020 10,784,170CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture2020 10,770,545Quantum dot devices2020 10,763,420Josephson Junction damascene fabrication2020 10,763,248Multi-layer silicon/gallium nitride semiconductor2020 10,763,347Quantum well stacks for quantum dot devices2020 10,763,349Quantum dot devices with modulation doped stacks2020 10,756,202Quantum dot device packages2020 10,748,961Interconnects below qubit plane by substrate bonding2020 10,748,960Interconnects below qubit plane by substrate doping2020 10,748,993Strain compensation in transistors2020 10,741,664Quantum dot devices with patterned gates2020 10,734,513Heterojunction TFETs employing an oxide semiconductor2020 10,734,482Quantum dot devices2020 10,727,339Selectively regrown top contact for vertical semiconductor devices2020 10,714,604Quantum dot devices with multiple dielectrics around fins2020 10,706,921Integrated 1T1R RRAM memory cell2020 10,693,008Cladding layer epitaxy via template engineering for heterogeneous integration on silicon2020 10,686,007Quantum circuit assemblies with at least partially buried transmission lines and capacitors2020 10,665,769Quantum circuit assemblies with vertically-stacked parallel-plate capacitors2020 10,665,770Fin strain in quantum dot devices2020 10,665,781Programmable metallization cell with alloy layer2020 10,658,586RRAM devices and their methods of fabrication2020 10,658,471Transition metal dichalcogenides (TMDCS) over III-nitride heteroepitaxial layers2020 10,644,113Quantum dot array devices2020 10,615,160Quantum dot array devices2020 10,593,756Quantum dot array devices2020 10,580,895Wide band gap transistors on non-native semiconductor substrates2020 10,573,809Resistive random access memory with deuterium2020 10,565,515Quantum circuit assemblies with triaxial cables2020 10,541,305Group III-N nanowire transistors2020 10,516,109Resistive memory cells and precursors thereof, methods of making the same, and devices including the same2019 10,516,104High retention resistive random access memory2019 10,497,871High retention resistive random access memory2019 10,490,727Gate arrangements in quantum dot devices2019 10,475,912Gate arrangements in quantum dot devices2019 10,475,706Making a defect free fin based device in lateral epitaxy overgrowth region2019 10,453,679Methods and devices integrating III-N transistor circuitry with Si transistor circuitry2019 10,439,134Techniques for forming non-planar resistive memory cells2019 10,424,620Non-volatile memory devices including integrated ballast resistor2019 10,418,487Non-planar gate all-around device and method of fabrication thereof2019 10,411,122Semiconductor device having group III-V material active region and graded gate dielectric2019 10,396,211Functional metal oxide based microelectronic devices2019 10,388,869Rare earth metal and metal oxide electrode interfacing of oxide memory element in resistive random access memory cell2019 10,388,733Strain compensation in transistors2019 10,388,848Donor- or acceptor-based spin qubits with isotopically purified materials2019 10,365,894Random number generator2019 10,361,353Sidewall metal spacers for forming metal gates in quantum devices2019 10,355,205Resistive memory cells including localized filamentary channels, devices including the same, and methods of making the same2019 10,347,834Wafer-scale integration of vacancy centers for spin qubits2019 10,347,767Transistor with a subfin layer2019 10,340,275Stackable thin film memory2019 10,325,774Wurtzite heteroepitaxial structures with inclined sidewall facets for defect propagation control in silicon CMOS-compatible semiconductor devices2019 10,319,646CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture2019 10,290,614Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits2019 10,263,079Apparatus and methods for forming a modulation doped non-planar transistor2019 10,263,074High voltage field effect transistors2019 10,249,490Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy2019 10,236,369Techniques for forming non-planar germanium quantum well devices2019 10,224,399Strain compensation in transistors2019 10,217,673Integrated circuit die having reduced defect group III-nitride structures and methods associated therewith2019 10,201,081Electronic fabric with incorporated chip and interconnect2019 10,186,580Semiconductor device having germanium active layer with underlying diffusion barrier layer2019 10,186,581Group III-N nanowire transistors2019 10,177,249Techniques for forming contacts to quantum well transistors2019 10,103,263Strained channel region transistors employing source and drain stressors and systems including the same2018 10,096,682III-N devices in Si trenches2018 10,096,709Aspect ratio trapping (ART) for fabricating vertical semiconductor devices2018 10,090,461Oxide-based three-terminal resistive switching logic devices2018 10,090,405Semiconductor device having group III-V material active region and graded gate dielectric2018 10,084,058Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains2018 10,074,718Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack2018 10,050,015Multi-device flexible electronics system on a chip (SOC) process integration2018 10,038,054Variable gate width for gate all-around transistors2018 10,032,911Wide band gap transistor on non-native semiconductor substrate2018 10,026,845Deep gate-all-around semiconductor device having germanium or group III-V active layer2018 10,020,371Contact techniques and configurations for reducing parasitic resistance in nanowire transistors2018 10,008,565Semiconductor devices with germanium-rich active layers and doped transition layers2018 9,972,686Germanium tin channel transistors2018 9,952,823Architecture for seamless integrated display system2018 9,947,780High electron mobility transistor (HEMT) and method of fabrication2018 9,923,087'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2018 9,911,807'Strain compensation in transistors'2018 9,905,651'GE and III-V channel semiconductor devices having maximized compliance and free surface relaxation'2018 9,876,014Germanium-based quantum well devices2018 9,865,684'Nanoscale structure with epitaxial film having a recessed bottom portion'2018 9,859,278'Bi-axial tensile strained GE channel for CMOS'2018 9,853,107Selective epitaxially grown III-V materials based devices2017 9,825,095'Hybrid phase field effect transistor'2017 9,818,870'Transistor structure with variable clad/core dimension for stress and bandgap'2017 9,818,847'Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface'2017 9,818,884'Strain compensation in transistors'2017 9,812,574'Techniques and configurations for stacking transistors of an integrated circuit device'2017 9,806,193'Stress in trigate devices using complimentary gate fill materials'2017 9,799,759'Techniques for forming non-planar germanium quantum well devices'2017 9,786,786'Non-planar quantum well device having interfacial layer and method of forming same'2017 9,755,062'III-N material structure for gate-recessed transistors'2017 9,748,371'Transition metal dichalcogenide semiconductor assemblies'2017 9,748,338'Preventing isolation leakage in III-V devices'2017 9,736,936'Electronic fabric with incorporated chip and interconnect'2017 9,704,981'Techniques for forming contacts to quantum well transistors'2017 9,698,265'Strained channel region transistors employing source and drain stressors and systems including the same'2017 9,691,857'Group III-N nanowire transistors'2017 9,691,848'Semiconductor devices with germanium-rich active layers and doped transition layers'2017 9,685,381'Integrating VLSI-compatible fin structures with selective epitaxial growth and fabricating devices thereon'2017 9,685,508'High voltage field effect transistors'2017 9,666,492'CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture'2017 9,666,708'III-N transistors with enhanced breakdown voltage'2017 9,666,583'Methods of containing defects for non-silicon device engineering'2017 9,660,085'Wide band gap transistors on non-native semiconductor substrates and methods of manufacture thereof'2017 9,653,548'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2017 9,653,680'Techniques for filament localization, edge effect reduction, and forming/switching voltage reduction in RRAM devices'2017 9,640,537'Non-silicon device heterolayers on patterned silicon substrate for CMOS by combination of selective and conformal epitaxy'2017 9,640,671'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2017 9,640,422'III-N devices in Si trenches'2017 9,640,646'Semiconductor device having group III-V material active region and graded gate dielectric'2017 9,634,007'Trench confined epitaxially grown device layer(s)'2017 9,627,384'Transistors with high concentration of boron doped germanium'2017 9,614,093'Strain compensation in transistors'2017 9,608,055'Semiconductor device having germanium active layer with underlying diffusion barrier layer'2017 9,590,089'Variable gate width for gate all-around transistors'2017 9,590,069'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2017 9,583,396'Making a defect free fin based device in lateral epitaxy overgrowth region'2017 9,577,190'Thermal management structure for low-power nonvolatile filamentary switch'2017 9,570,614'Ge and III-V channel semiconductor devices having maximized compliance and free surface relaxation'2017 9,564,490'Apparatus and methods for forming a modulation doped non-planar transistor'2017 9,530,878'III-N material structure for gate-recessed transistors'2016 9,502,568'Non-planar quantum well device having interfacial layer and method of forming same'2016 9,490,329'Semiconductor devices with germanium-rich active layers and doped transition layers'2016 9,478,635'Germanium-based quantum well devices'2016 9,461,160'Non-planar III-N transistor'2016 9,461,141'Contact techniques and configurations for reducing parasitic resistance in nanowire transistors'2016 9,455,343'Hybrid phase field effect transistor'2016 9,450,092'Stress in trigate devices using complimentary gate fill materials'2016 9,443,936'Quantum well MOSFET channels having lattice mismatch with metal source/drains, and conformal regrowth source/drains'2016 9,397,188'Group III-N nanowire transistors'2016 9,397,166'Strained channel region transistors employing source and drain stressors and systems including the same'2016 9,391,181'Lattice mismatched hetero-epitaxial film'2016 9,374,509'Wearable imaging sensor for communications'2016 9,356,099'Techniques for forming contacts to quantum well transistors'2016 9,343,574'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2016 9,337,291'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2016 9,306,068'Stain compensation in transistors'2016 9,293,546'Vertical tunneling negative differential resistance devices'2016 9,263,557'Techniques for forming non-planar germanium quantum well devices'2016 9,257,346'Apparatus and methods for forming a modulation doped non-planar transistor'2016 9,252,275'Non-planar gate all-around device and method of fabrication thereof'2016 9,253,884'Electronic fabric with incorporated chip and interconnect'2016 9,245,989'High voltage field effect transistors'2016 9,240,410'Group III-N nanowire transistors'2016 9,236,476'Techniques and configuration for stacking transistors of an integrated circuit device'2016 9,224,754'Stress in trigate devices using complimentary gate fill materials'2015 9,219,135'Germanium-based quantum well devices'2015 9,209,290'III-N material structure for gate-recessed transistors'2015 9,159,823'Strain compensation in transistors'2015 9,159,787'Semiconductor devices with germanium-rich active layers and doped transition layers'2015 9,153,671'Techniques for forming non-planar germanium quantum well devices'2015 9,136,343'Deep gate-all-around semiconductor device having germanium or group III-V active layer'2015 9,123,567'CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture'2015 9,123,790'Contact techniques and configurations for reducing parasitic resistance in nanowire transistors'2015 9,112,028'Methods of containing defects for non-silicon device engineering'2015 9,099,490'Self-aligned structures and methods for asymmetric GaN transistors and enhancement mode operation'2015 9,087,887'Non-planar quantum well device having interfacial layer and method of forming same'2015 9,054,190'Methods of containing defects for non-silicon device engineering'2015 9,048,266'Apparatus and methods for improving parallel conduction in a quantum well device'2015 9,035,387'Multi-gate device'2015 9,029,835'Epitaxial film on nanoscale structure'2015 9,018,680'Non-planar semiconductor device having active region with multi-dielectric gate stack'2015 8,987,794'Non-planar gate all-around device and method of fabrication thereof'2015 8,987,091'III-N material structure for gate-recessed transistors'2015 8,946,679'Vertical tunneling negative differential resistance devices'2015 8,941,128'Passivation layer for flexible display'2015 8,901,537'Transistors with high concentration of boron doped germanium'2014 8,890,264'Non-planar III-V field effect transistors with conformal metal gate electrode and nitrogen doping of gate dielectric interface'2014 8,883,573'Isolation for nanowire devices'2014 8,872,225'Defect transferred and lattice mismatched epitaxial film'2014 8,853,067'Method of isolating nanowires from a substrate'2014 8,846,480'Carrier mobility in surface-channel transistors, apparatus made therewith, and system containing same'2014 8,823,059'Non-planar semiconductor device having group III-V material active region with multi-dielectric gate stack'2014 8,809,836'Techniques for forming contacts to quantum well transistors'2014 8,785,907'Epitaxial film growth on patterned substrate'2014 8,785,909'Non-planar semiconductor device having channel region with low band-gap cladding layer'2014 8,765,563'Trench confined epitaxially grown device layer(s)'2014 8,748,269'Quantum-well-based semiconductor devices'2014 8,748,940'Semiconductor devices with germanium-rich active layers and doped transition layers'2014 8,741,733'Stress in trigate devices using complimentary gate fill materials'2014 8,716,751'Methods of containing defects for non-silicon device engineering'2014 8,710,490'Semiconductor device having germanium active layer with underlying parasitic leakage barrier layer'2014 8,674,448'Trigate static random-access memory with independent source and drain engineering, and devices made therefrom'2014 8,659,058'Methods of forming nickel sulphide film on a semiconductor device'2014 8,633,470'Techniques and configurations to impart strain to integrated circuit devices'2014 8,633,471'Apparatus and methods for forming a modulation doped non-planar transistor'2014 8,592,803'Germanium-based quantum well devices'2013 8,575,653'Non-planar quantum well device having interfacial layer and method of forming same'2013 8,575,596'Non-planar germanium quantum well devices'2013 8,541,773'Vertical tunneling negative differential resistance devices'2013 8,536,621'Quantum-well-based semiconductor devices'2013 8,525,151'Apparatus and methods for improving parallel conduction in a quantum well device'2013 8,525,162'Method of isolating nanowires from a substrate'2013 8,501,508'Method of forming quantum well mosfet channels having uni-axial strains caused by metal source/drains'2013 8,384,128'Carrier mobility in surface-channel transistors, apparatus made therewith, and systems containing same'2013 8,378,334'Low power floating body memory cell based on low-bandgap-material quantum well'2013 8,368,052'Techniques for forming contacts to quantum well transistors'2013 8,362,566'Stress in trigate devices using complimentary gate fill materials'2013 8,361,871'Trigate static random-access memory with independent source and drain engineering, and devices made therefrom'2013 8,350,291'Modulation-doped multi-gate devices'2013 8,344,425'Multi-gate III-V quantum well structures'2013 8,324,661'Quantum well transistors with remote counter doping'2012 8,283,653'Non-planar germanium quantum well devices'2012 8,278,687'Semiconductor heterostructures to reduce short channel effects'2012 8,269,209'Isolation for nanowire devices'2012 8,258,543'Quantum-well-based semiconductor devices'2012 8,258,498'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2012 8,242,001'Apparatus and methods for improving parallel conduction in a quantum well device'2012 8,227,833'Dual layer gate dielectrics for non-silicon semiconductor devices'2012 8,211,771'Multiple-gate transistors and processes of making same'2012 8,193,523'Germanium-based quantum well devices'2012 8,168,508'Method of isolating nanowires from a substrate'2012 8,148,772'Recessed channel array transistor (RCAT) structures'2012 8,129,749'Double quantum well structures for transistors'2012 8,120,063'Modulation-doped multi-gate devices'2012 8,120,073'Trigate transistor having extended metal gate electrode'2012 8,115,235'Modulation-doped halo in quantum well field-effect transistors, apparatus made therewith, and methods of using same'2012 8,093,584'Self-aligned replacement metal gate process for QWFET devices'2012 8,088,665'Method of forming self-aligned low resistance contact layer'2012 8,080,820'Apparatus and methods for improving parallel conduction in a quantum well device'2011 8,063,447'Multiple-gate transistors and processes of making same'2011 8,030,163'Reducing external resistance of a multi-gate device using spacer processing techniques'2011 8,030,197'Recessed channel array transistor (RCAT) in replacement metal gate (RMG) logic flow'2011 8,022,487'Increasing body dopant uniformity in multi-gate transistor devices'2011 8,017,933'Compositionally-graded quantum-well channels for semiconductor devices'2011 8,012,816'Double pass formation of a deep quantum well in enhancement mode III-V devices'2011 7,964,866'Low power floating body memory cell based on low bandgap material quantum well'2011 7,964,490'Methods of forming nickel sulfide film on a semiconductor device'2011 7,947,971'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2011 7,915,642'Apparatus and methods for forming a modulation doped non-planar transistor'2011 7,898,023'Recessed channel array transistor (RCAT) structures'2011 7,892,902'Group III-V devices with multiple spacer layers'2011 7,884,354'Germanium on insulator (GOI) semiconductor substrates'2011 7,868,318'Quantum well field-effect transistors with composite spacer structures, apparatus made therewith, and methods of using same'2011 7,851,790'Isolated Germanium nanowire on Silicon fin'2010 7,833,889'Apparatus and methods for improving multi-gate device performance'2010 7,825,437'Unity beta ratio tri-gate transistor static random access memory (SRAM)'2010 7,820,512'Spacer patterned augmentation of tri-gate transistor gate length'2010 7,800,166'Recessed channel array transistor (RCAT) structures and method of formation'2010 7,777,282'Self-aligned tunneling pocket in field-effect transistors and processes to form same'2010 7,763,943'Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin'2010 7,759,142'Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains'2010 7,629,643'Independent n-tips for multi-gate transistors'2009

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2009–2021Patents assigned to INTEL CORP (283)· patent assignee history

2009–2021Based in Portland, OR, US· patent location history

2011–2019Patents assigned to PILLARISETTY RAVI (83)· patent assignee history

2011–2019Patents assigned to RADOSAVLJEVIC MARKO (56)· patent assignee history

2012–2019Patents assigned to DEWEY GILBERT (45)· patent assignee history

2012–2019Patents assigned to MUKHERJEE NILOY (38)· patent assignee history

2017Based in Potland, OR, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	283	2009–2021
PILLARISETTY RAVIself	83	2011–2019
RADOSAVLJEVIC MARKO	56	2011–2019
DEWEY GILBERT	45	2012–2019
MUKHERJEE NILOY	38	2012–2019

Locations

Location	Patents	Span
Portland, OR, US	284	2009–2021
Potland, OR, US	1	2017