Inventor
Cheng-Ting Chen
Inventor
Taichung, TW
Overview
Patents· 32 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1029%
H01LSemiconductor devices27%
H05KPrinted circuits9%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%
B23KSoldering or unsoldering3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
B24BMachines, devices, or processes for grinding or polishing2%
G05BControl or regulating systems in general2%
H01RElectrically-conductive connections2%
H05BElectric heating2%
PatentTitleYear
10,879,203Stud bump structure for semiconductor package assemblies202010,784,221Method of processing solder bump by vacuum annealing202010,566,261Integrated fan-out packages with embedded heat dissipation structure202010,535,644Manufacturing method of package on package structure202010,534,353System and method to reduce pre-back-grinding process defects202010,512,124Warpage control in the packaging of integrated circuits201910,504,815Integrated fan-out packages with embedded heat dissipation structure201910,062,659System and method for an improved fine pitch joint201810,015,888Interconnect joint protective layer apparatus and method20189,935,044Semiconductor packaging and manufacturing method thereof20189,799,631'Semiconductor packaging structure and method'20179,768,137'Stud bump structure for semiconductor package assemblies'20179,627,234'Method and apparatus for localized and controlled removal of material from a substrate'20179,583,464'Semiconductor packaging structure and method'20179,538,582'Warpage control in the packaging of integrated circuits'20179,437,564'Interconnect structure and method of fabricating same'20169,418,955'Plasma treatment for semiconductor devices'20169,412,689'Semiconductor packaging structure and method'20169,373,603'Reflow process and tool'20169,355,927'Semiconductor packaging and manufacturing method thereof'20169,281,288'System and method for fine pitch PoP structure'20169,263,839'System and method for an improved fine pitch joint'20169,230,935'Package on package structure and method of manufacturing the same'20168,987,058'Method for wafer separation'20158,901,726'Package on package structure and method of manufacturing the same'20148,878,352'Semiconductor packaging structure and method'20148,674,496'System and method for fine pitch PoP structure'20148,629,053'Plasma treatment for semiconductor devices'20148,571,699'System and method to reduce pre-back-grinding process defects'20138,440,503'Methods for performing reflow in bonding processes'20136,692,985'Solar cell substrate with thin film polysilicon'20046,277,667'Method for fabricating solar cells'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001Based in Taipei, TW· patent location history
2004Based in Taoyuan, TW· patent location history
2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (11)· patent assignee history
2013–2017Patents assigned to CHEN CHENG-TING (7)· patent assignee history
2013–2017Patents assigned to LIU CHUNG-SHI (7)· patent assignee history
2013–2017Patents assigned to CHENG MING-DA (5)· patent assignee history
2013–2020Based in Taichung, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (17)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 17 | 2016–2020 |
| TAIWAN SEMICONDUCTOR MFG | 11 | 2013–2016 |
| CHEN CHENG-TINGself | 7 | 2013–2017 |
| LIU CHUNG-SHI | 7 | 2013–2017 |
| CHENG MING-DA | 5 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Taichung, TW | 30 | 2013–2020 |
| Taoyuan, TW | 1 | 2004 |
| Taipei, TW | 1 | 2001 |