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Inventor

Ronnie M. Harrison

Inventor
Boise, ID, US

Overview

43→
Patents
1976–2013
Patent span
Electricity
Primary field (CPC H)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores24%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses24%
H03KPulse technique19%
H03DDemodulation or transference of modulation from one carrier to another9%
G06FElectric digital data processing8%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems4%
H04LTransmission of digital information, e.g. telegraphic communication3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
Y10TTechnical subjects covered by former us classification3%
H04NPictorial communication, e.g. television2%
PatentTitleYear
8,565,008'Method and apparatus for generating a sequence of clock signals'20138,433,023'Method and apparatus for generating a phase dependent control signal'20138,107,580'Method and apparatus for generating a phase dependent control signal'20127,889,593'Method and apparatus for generating a sequence of clock signals'20117,746,959'Method and system for generating reference voltages for signal receivers'20107,602,876'Method and apparatus for generating a phase dependent control signal'20097,577,212'Method and system for generating reference voltages for signal receivers'20097,418,071'Method and apparatus for generating a phase dependent control signal'20087,415,404'Method and apparatus for generating a sequence of clock signals'20087,159,092'Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same'20077,145,376'Method and circuitry for reducing duty cycle distortion in differential delay lines'20067,082,678'Method of fabricating an integrated circuit package'20067,055,241'Method of fabricating an integrated circuit package'20067,042,265'Interlaced delay-locked loops for controlling memory-circuit timing'20067,016,451'Method and apparatus for generating a phase dependent control signal'20066,954,097'Method and apparatus for generating a sequence of clock signals'20056,952,462'Method and apparatus for generating a phase dependent control signal'20056,931,086'Method and apparatus for generating a phase dependent control signal'20056,911,807'Method and circuit for limiting a pumped voltage'20056,842,399'Delay lock loop circuit useful in a synchronous system and associated methods'20056,806,754'Method and circuitry for reducing duty cycle distortion in differential delay lines'20046,801,989'Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same'20046,781,419'Method and system for controlling the duty cycle of a clock signal'20046,777,995'Interlaced delay-locked loops for controlling memory-circuit timing'20046,753,675'Method and circuit for limiting a pumped voltage'20046,750,639'Method and circuit for limiting a pumped voltage'20046,744,281'Method and system for controlling the duty cycle of a clock signal'20046,690,148'Method and circuit for limiting a pumped voltage'20046,680,874'Delay lock loop circuit useful in a synchronous system and associated methods'20046,535,032'Data receiver technology'20036,470,060'Method and apparatus for generating a phase dependent control signal'20026,424,178'Method and system for controlling the duty cycle of a clock signal'20026,362,426'Radiused leadframe'20026,249,165'Interlaced delay-locked loops for controlling memory-circuit timing'20016,201,424'Synchronous clock generator including a delay-locked loop signal loss detector'20016,173,432'Method and apparatus for generating a sequence of clock signals'20016,119,242'Synchronous clock generator including a false lock detector'20006,011,732'Synchronous clock generator including a compound delay-locked loop'20005,940,609'Synchronous clock generator including a false lock detector'19995,926,047'Synchronous clock generator including a delay-locked loop signal loss detector'19995,920,518'Synchronous clock generator including delay-locked loop'19994,062,041'Input voltage controlled oscillator circuit for a television signal time base corrector'19773,993,982'Sequence control unit for a television time base corrector'1976

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1976–1977Patents assigned to CONS VIDEO SYSTEMS (2)· patent assignee history
1976–1977Based in San Jose, CA, US· patent location history
1999–2010Patents assigned to MICRON TECHNOLOGY INC (35)· patent assignee history
1999Patents assigned to MICORN TECHNOLOGY INC (1)· patent assignee history
1999–2013Based in Boise, ID, US· patent location history
2011–2013Patents assigned to ROUND ROCK RES LLC (4)· patent assignee history
2012–2013Patents assigned to HARRISON RONNIE M (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC351999–2010
ROUND ROCK RES LLC42011–2013
HARRISON RONNIE Mself32012–2013
CONS VIDEO SYSTEMS21976–1977
MICORN TECHNOLOGY INC11999
Locations
LocationPatentsSpan
Boise, ID, US411999–2013
San Jose, California, US21976–1977