Interlaced delay-locked loops for controlling memory-circuit timing

A clock-generation circuit comprising: a first delay element configured to provide a first nominal delay; a second delay element configured to provide a second nominal delay different from the first nominal delay; and a differential phase amplifier having first and second inputs connected respectively to the first and second delay elements and having an output connected to control only one of the first and second delay elements.

A clock-generation circuit comprising: a first delay line including a chain of two or more delay elements, each configured to provide a first nominal delay; a second delay line including a chain of two or more delay elements, at least one of which is configured to provide the first nominal delay and at least one of which is configured to provide a second nominal delay different from the first nominal delay; and a differential phase amplifier having first and second inputs connected respectively to one of the delay elements configured to provide the first nominal delay and to the one delay element configured to provide the second nominal delay and having an output connected to control only one of the first and second nominal delays.

A clock-generation circuit comprising: first delay means for providing a first nominal delay; second delay means for providing a second nominal delay different from the first nominal delay; and a differential phase amplifier having first and second inputs connected respectively to the first and second delay elements and an output connected to control only one of the first and second nominal delays.

A clock-generation circuit for generating a set of clock signals each approximately delayed relative a reference clock signal by a multiple of a delay period, the circuit comprising: a first delay line having an input for receiving the reference clock signal and two or more delay elements for outputting respective even clock signals, each approximately delayed relative to the reference clock signal by an even multiple of the delay period; a second delay line having an input for receiving the reference clock signal and one or more delay elements for outputting respective odd clock signals, each approximately delayed relative tu the reference clock signal by an odd multiple of the delay period and at least one clock signal delayed relative the reference clock by an even multiple of the delay period; and a differential phase amplifier responsive to a phase difference between one of the even clock signals and the one clock signal of the second delay line delayed by an even multiple of the delay period to control one or more delay elements of the second delay line.

The clock-generation circuit of clam 8, wherein the differential phase amplifier comprises: a phase detector including: first and second inputs for receiving first and second signals; and first and second pairs of NAND gates for providing respective first and second pairs of complementary outputs based on a phase relationship of the first and second signals; and a charge pump responsive to the first and second pairs of complementary outputs to provide a signal representative of the phase relationship of the first and second signals, the charge pump including means for overriding an effect of the first and second pairs of complementary signals on the signal representative of the phase relationship.

A clock-generation circuit comprising: a first continuously adjustable delay element configured to provide a first nominal delay; a second continuously adjustable delay element configured to provide a second nominal delay different from the first nominal delay; and a differential phase amplifier having a first input connected to an output of the first delay element, a second input connected to an output of the second delay element, and an output connected to a control node of only one of the first and second delay elements.

A clock-generation circuit comprising: a first delay circuit having an input for receiving a reference clock signal and a first plurality of outputs, each providing an output signal delayed by an even multiple of a delay period relative to the reference clock signal; a second delay circuit having an input for receiving the reference clock signal and a second plurality of outputs, each providing an output signal delayed by a multiple of the delay period relative to the reference clock signal; and a differential phase amplifier coupled to the first delay circuit and the second delay circuit and responsive to a phase relationship between one of the first outputs and one of the second outputs.

A clock-generation circuit for generating a set of clock signals each approximately delayed relative a reference clock signal by an integral multiple of a delay period, the circuit comprising: first means for receiving the reference clock signal and outputting respective first clock signals, each approximately delayed relative the reference clock signal by a multiple of the delay period; second means for receiving the reference clock signal and outputting respective second clock signals, each approximately delayed relative the reference clock signal by a multiple of the delay period; and third means responsive to a phase difference between one of the first clock signals and one of the second clock signals to control one or more delay elements of the second delay line.

A clock-generation circuit comprising: one or more first delay elements which provide a first nominal delay; one or more second delay elements which provide a second nominal delay different from the first nominal delay; and a differential phase amplifier having first and second inputs coupled respectively to at least one of the first delay elements and to one of the second delay elements and an output coupled to control only one of the first and second nominal delays.

A circuit comprising: one or more first delay elements which provide a first nominal delay; one or more second delay elements which provide a second nominal delay different from the first nominal delay; and a differential phase amplifier responsive to at least one of the first delay elements and to one of the second delay elements to control only one or more of the second delay elements.

A clock-generation circuit for generating a set of clock signals each approximately delayed relative a reference clock signal by an integral multiple of a nominal delay period, the circuit comprising: a first delay line having an input for receiving the reference clock signal and two or more delay elements for outputting respective even clock signals, each approximately delayed relative to the reference clock signal by an even multiple of the delay period; and a second delay line having an input for receiving the reference clock signal and two or more delay elements, one or more of which output respective clock signals delayed relative to the reference clock signal by an odd multiple of the delay period and at least one of which outputs a clock signal delayed relative the reference clock signal by an even multiple of the delay period.

A clock-generation circuit for generating a plurality of clock signals, the circuit composing: a first delay line having an input for receiving a reference clock signal and two or more controllable delay elements for outputting respective even clock signals, each delayed relative to the reference clock signal by approximately an even number of delay periods; a second delay line having an input for receiving the reference clock signal, having one or more controllable delay elements for outputting respective odd clock signals each delayed relative to the reference clock signal by approximately an odd number of delay periods, and having at least one controllable delay elements for outputting a clock signal delayed relative the reference clock signal by approximately an even number of delay periods; a first differential phase amplifier responsive to a phase difference between one of the even clock signals and a clock signal based on the reference clock signal to control one or more delay elements of the first delay line and one or more delay elements of the second delay line; and a second differential phase amplifier responsive to a phase difference between one of the even clock signals and the one clock signal of the second delay delayed an even number of delay periods.

A memory controller comprising: a first delay element configured to provide a first nominal delay; a second delay element configured to provide a second nominal delay different from the first nominal delay; and a differential phase amplifier having a first input connected to an output of the first delay element, a second input connected to an output of the second delay element, and an output connected to a control node of only one of the first and second delay elements.

A system comprising: a processor; one or more integrated-circuit memories; one or more input, output, or storage devices; and a memory controller coupled to the processor and to the one or more integrated-circuit memories, the memory controller comprising: a first delay element configured to provide a first nominal delay; a second delay element configured to provide a second nominal delay different from the first nominal delay; and a differential phase amplifier having a first input connected to an output of the first delay element, a second inputs connected to an output of the second delay element, and an output connected to a control node of only one of the first and the second delay elements.

A system comprising: a processor; and a memory circuit coupled to the processor and comprising: a first delay element configured to provide a first nominal delay; a second delay element configured to provide a second nominal delay different from the first nominal delay; and a differential phase amplifier having a first input connected to an output of the first delay element, a second inputs connected to an output of the second delay element, and an output connected to a control node of only one of the first and the second delay elements.

A method of generating clock signals, comprising: generating a first set of two or more even clock signals, each delayed relative a reference clock signal by an even multiple of a first delay period; generating a second set of one or more odd clock signals, of which one or more are delayed relative the reference clock signal by an odd multiple of the first delay period and at least one is delayed by an even multiple of the first delay period; and synchronizing the second set of clock signals to one or more of the first set of clock signals.

A method of generating clock signals, comprising: synchronizing a first set of two or more even clock signals to a reference clock signal, with each even clock signal delayed relative the reference clock signal by an even multiple of a delay period; and synchronizing a second set of one or more odd clock signals to one or more of the even clock signals, with each odd clock signal delayed relative the reference clock signal by an odd multiple of the delay period.

A method of generating one or more clock signals delayed relative a reference clock signal by an integral multiple of a desired nominal delay period, the method comprising: providing a first delay-locked loop comprising a chain of two or more delay elements, each providing a first nominal delay and a respective clock signal; providing a second delay-locked loop comprising one or more delay elements, each providing a respective clock signal and at least one providing a second nominal delay different from the first nominal delay by an amount substantially equal to the desired nominal delay period; and synchronizing one or more delay elements of the second delay loop to a clock signal of the first delay-locked loop, thereby causing one or more clock signals of the second delay-locked loop to be delayed relative to one or more of the output signals of the first delay-locked loop by the desired nominal delay period.

A method of generating a plurality of clock signals, the circuit comprising: applying a reference clock signal to a first delay line having two or more controllable delay elements for outputting respective even clock signals, each sequentially delayed relative to the reference clock signal by approximately an even number of delay periods; applying the reference clock signal to a second delay line having two or more controllable delay elements for outputting respective clock signals, one or more of which are delayed relative to the reference clock signal by approximately an odd number of delay periods and at least one of which is delayed relative to the reference clock signal by approximately an even number of delay periods; adjusting one or more of the controllable delay elements of the first delay line based on a phase difference between one of the even clock signals and the reference clock signal; and adjusting one or more of the controllable delay elements of the second delay line based on a phase difference between one of the even clock signals and one of the clock signals in the second delay line.

A clock-generation circuit comprising: one or more first delay elements which provide a first nominal delay; one or more second delay elements which provide a second nominal delay different from the first nominal delay; and a differential phase amplifier coupled to at least one of the first delay elements and to one of the second delay elements; wherein the one or more first delay elements form at least part of a first delay line which is responsive to a reference clock signal to provide a set of even clock signals, each delayed an even multiple of a nominal delay relative to the reference clock signal and wherein the one or more second delay elements form at least part of a second delay line which is responsive to the reference clock signal to provide a set of odd clock signals, each delayed an odd multiple of the nominal delay relative to the reference clock signal.