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Inventor

Mark A. Helm

Inventor
Boise, ID, US

Overview

92→
Patents
1996–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 92 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores26%
H10DInorganic electric semiconductor devices23%
H10BElectronic memory devices17%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
G06FElectric digital data processing8%
Y10TTechnical subjects covered by former us classification4%
H01LSemiconductor devices3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
H03MCoding2%
PatentTitleYear
11,029,861Sense flags in a memory device202110,685,702Memory array reset read operation202010,593,624Three dimensional storage cell array with highly dense and scalable word line design approach202010,431,310Boosted channel programming of memory201910,409,506Sense flags in a memory device201910,289,484Apparatuses and methods for generating probabilistic information with current integration sensing201910,248,500Apparatuses and methods for generating probabilistic information with current integration sensing201910,186,325Method and apparatus for shielded read to reduce parasitic capacitive coupling201910,126,967Sense operation flags in a memory device201810,115,457Threshold voltage distribution determination by sensing common source line currents201810,090,053Apparatus, systems, and methods to operate a memory201810,043,751Three dimensional storage cell array with highly dense and scalable word line design approach201810,014,061Methods and apparatus having multiple select gates of different ranges of threshold voltages connected in series with memory cells20189,972,391Apparatus, systems, and methods to operate a memory20189,947,418Boosted channel programming of memory20189,754,683'Method and system to obtain state confidence data using multistrobe read of a non-volatile memory'20179,620,229'Three dimensional memory control circuitry'20179,607,692'Threshold voltage distribution determination'20179,576,674'Memory cell sensing'20179,552,888'Methods, devices, and systems for data sensing'20179,519,582'Sense operation flags in a memory device'20169,431,421'Data line arrangement and pillar arrangement in apparatuses'20169,330,777'Memory program disturb reduction'20169,251,860'Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods'20169,251,908'Memory kink checking'20169,202,536'Three dimensional memory control circuitry'20159,159,736'Data line arrangement and pillar arrangement in apparatuses'20159,135,998'Sense operation flags in a memory device'20159,070,442'Memory devices with local and global devices at substantially the same level above stacked tiers of memory cells and methods'20159,047,972'Methods, devices, and systems for data sensing'20159,001,577'Memory cell sensing'20158,982,625'Memory program disturb reduction'20158,902,650'Memory devices and operating methods for a memory device'20148,804,419'Memory kink checking'20148,780,626'Sense operation in a memory device'20148,711,615'Memory kink checking'20148,647,949'Structure and method of fabricating a transistor having a trench gate'20148,631,288'Methods, devices, and systems for data sensing in a memory system'20148,572,335'Copyback optimization for memory system'20138,565,018'Reducing effects of erase disturb in a memory device'20138,542,542'Non-volatile memory cell healing'20138,482,975'Memory kink checking'20138,374,028'Sense operation in a memory device'20138,238,170'Non-volatile memory cell healing'20128,203,876'Reducing effects of erase disturb in a memory device'20128,185,706'Copyback optimization for memory system'20128,053,321'Formation of standard voltage threshold and low voltage threshold MOSFET devices'20117,879,665'Structure and method of fabricating a transistor having a trench gate'20117,755,146'Formation of standard voltage threshold and low voltage threshold MOSFET devices'20107,701,780'Non-volatile memory cell healing'20107,696,579'Formation of standard voltage threshold and low voltage threshold MOSFET devices'20107,563,679'Reduction of field edge thinning in peripheral devices'20097,554,846'Select gate transistors and methods of operating the same'20097,499,325'Flash memory device with improved erase operation'20097,439,140'Formation of standard voltage threshold and low voltage threshold MOSFET devices'20087,413,946'Formation of standard voltage threshold and low voltage threshold MOSFET devices'20087,358,561'Source lines for NAND memory devices'20087,332,419'Structure and method of fabricating a transistor having a trench gate'20087,304,353'Formation of standard voltage threshold and low voltage threshold MOSFET devices'20077,279,710'Structure and method of fabricating a transistor having a trench gate'20077,274,065'Source lines for NAND memory devices'20077,265,012'Formation of standard voltage threshold and low voltage threshold MOSFET devices'20077,262,102'Reduction of field edge thinning in peripheral devices'20077,241,662'Reduction of field edge thinning in peripheral devices'20077,202,129'Source lines for NAND memory devices'20077,189,607'Formation of standard voltage threshold and low voltage threshold MOSFET devices'20077,176,086'Interconnecting conductive layers of memory devices'20077,141,850'Gated semiconductor assemblies and methods of forming gated semiconductor assemblies'20067,112,488'Source lines for NAND memory devices'20066,949,795'Structure and method of fabricating a transistor having a trench gate'20056,861,697'Interconnecting conductive layers of memory devices'20056,849,492'Method for forming standard voltage threshold and low voltage threshold MOSFET devices'20056,759,298'Methods of forming an array of flash field effect transistors and circuitry peripheral to such array'20046,756,634'Gated semiconductor assemblies'20046,746,921'Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array'20046,645,814'Method of forming an array of FLASH field effect transistors and circuitry peripheral to such array'20036,647,542'Efficient fabrication process for dual well type structures'20036,635,530'Methods of forming gated semiconductor assemblies'20036,396,100'Efficient fabrication process for dual well type structures'20026,358,787'Method of forming CMOS integrated circuitry'20026,268,250'Efficient fabrication process for dual well type structures'20016,261,888'Method of forming CMOS integrated circuitry'20016,124,616'Integrated circuitry comprising halo regions and LDD regions'20006,074,924'Method of forming CMOS integrated circuitry'20006,004,854'Method of forming CMOS integrated circuitry'19995,970,335'Semiconductor processing method of forming complementary n-type doped and p-type doped active regions within a semiconductor substrate'19995,776,806'Method of forming CMOS integrated circuitry having halo regions'19985,747,855'CMOS integrated circuitry with Halo and LDD regions'19985,683,927'Method of forming CMOS integrated circuitry'19975,624,863'Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate'19975,534,449'Methods of forming complementary metal oxide semiconductor (CMOS) integrated circuitry'19965,523,258'Method for avoiding lithographic rounding effects for semiconductor fabrication'1996

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1996–2021Patents assigned to MICRON TECHNOLOGY INC (76)· patent assignee history
1996–2014Based in Boise, ID, US· patent location history
2009–2020Patents assigned to INTEL CORP (7)· patent assignee history
2012–2017Patents assigned to HELM MARK (7)· patent assignee history
2012–2015Patents assigned to HELM MARK A (7)· patent assignee history
2012–2015Patents assigned to GODA AKIRA (4)· patent assignee history
2012–2021Based in Santa Cruz, CA, US· patent location history
2018Based in San Jose, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
MICRON TECHNOLOGY INC761996–2021
HELM MARKself72012–2017
HELM MARK Aself72012–2015
INTEL CORP72009–2020
GODA AKIRA42012–2015
Locations
LocationPatentsSpan
Boise, ID, US491996–2014
Santa Cruz, California, US422012–2021
San Jose, California, US12018