Inventor
Mirng-Ji Lii
Inventor
Jhudong Township, TW
Overview
Patents· 167 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1043%
H01LSemiconductor devices29%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
H10DInorganic electric semiconductor devices6%
H05KPrinted circuits3%
B23KSoldering or unsoldering2%
Y10TTechnical subjects covered by former us classification2%
B21DWorking or processing of sheet metal or metal tubes, rods or profiles without essentially removing material1%
H10FInorganic semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
PatentTitleYear
11,133,274Fan-out interconnect structure and method for forming same202111,101,233Semiconductor device and method for forming the same202111,075,173Semiconductor device and method of forming same202111,069,573Wafer level package structure and method of forming same202111,024,593Metal bumps and method forming same202111,018,065Semiconductor device structure with magnetic element in testing region202111,004,685Multi-layer structures and methods of forming202110,985,124Semiconductor structure and manufacturing method thereof202110,910,466Process for tuning via profile in dielectric material202110,867,949Substrate design for semiconductor packages and method of forming same202010,861,811Connector structure and method of forming same202010,825,798Packages with stacked dies and methods of forming the same202010,714,359Substrate design for semiconductor packages and method of forming same202010,700,001Forming bonding structures by using template layer as templates202010,700,025Fan-out interconnect structure and method for forming same202010,643,861Methods for making multi-die package with bridge layer202010,559,546Package on package structure and method for forming the same202010,522,481Post-passivation interconnect structure201910,510,731Package-on-package (PoP) structure including stud bulbs201910,388,620Connector structure and method of forming same201910,354,983Integrated circuit package and methods of forming same201910,319,695Semiconductor device and bump formation process201910,319,607Package-on-package structure with organic interposer201910,319,692Semiconductor structure and manufacturing method thereof201910,312,204System and method for an improved interconnect structure201910,276,525Package structure and method of fabricating the same201910,269,904Semiconductor structure and manufacturing method thereof201910,269,489Programmable inductor201910,177,104Package on package structure and method for forming the same201910,163,734Method for manufacturing semiconductor structure201810,163,842Semiconductor structure and manufacturing method thereof201810,157,893Package-on-package (PoP) structure including stud bulbs201810,153,243Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices201810,147,693Methods for stud bump formation201810,121,749Method of fabricating a post-passivation interconnect structure201810,090,345Interconnect structure for CIS flip-chip bonding and methods for forming the same201810,062,659System and method for an improved fine pitch joint201810,056,267Substrate design for semiconductor packages and method of forming same201810,056,345Conical-shaped or tier-shaped pillar connections201810,049,894Package structures and methods for forming the same201810,043,770System and method for an improved interconnect structure201810,026,671Substrate design for semiconductor packages and method of forming same201810,020,286Package on package devices and methods of packaging semiconductor dies20189,984,999Packages with stacked dies and methods of forming the same20189,935,047Bonding structures and methods forming the same20189,935,073Semiconductor structure and manufacturing method of the same20189,935,038Semiconductor device packages and methods20189,935,081Hybrid interconnect for chip stacking20189,917,035'Bump-on-trace interconnection structure for flip-chip packages'20189,870,946'Wafer level package structure and method of forming same'20189,831,140Wafer having pad structure20179,812,427'Package on-package (PoP) structure including stud bulbs'20179,768,090'Substrate design for semiconductor packages and method of forming same'20179,768,105'Rigid interconnect structures in package-on-package assemblies'20179,728,427'Method for manufacturing semiconductor structure'20179,711,470'Package on package structure and method for forming the same'20179,666,530'Semiconductor device'20179,653,442'Integrated circuit package and methods of forming same'20179,653,443'Thermal performance structure for semiconductor packages and method of forming same'20179,646,943'Connector structure and method of forming same'20179,646,923'Semiconductor devices, methods of manufacture thereof, and packaged semiconductor devices'20179,640,521'Multi-die package with bridge layer and method for making the same'20179,633,965'Semiconductor structure and manufacturing method of the same'20179,633,870'System and method for an improved interconnect structure'20179,633,963'Packaging devices and methods of manufacture thereof'20179,613,914'Post-passivation interconnect structure'20179,559,076'Package having substrate with embedded metal trace overlapped by landing pad'20179,543,259'Semiconductor structure with oval shaped conductor'20179,536,850'Package having substrate with embedded metal trace overlapped by landing pad'20179,536,818'Semiconductor package and method of forming the same'20179,530,757'Single mask package apparatus'20169,530,759'3D package with through substrate vias'20169,502,394'Package on-Package (PoP) structure including stud bulbs and method'20169,498,851'Methods for forming apparatus for stud bump formation'20169,461,106'MIM capacitor and method forming the same'20169,449,941'Connecting function chips to a package to form package-on-package'20169,443,812'Semiconductor device with post-passivation interconnect structure and method of forming the same'20169,425,136'Conical-shaped or tier-shaped pillar connections'20169,418,978'Method of forming package-on-package (PoP) structure having a chip package with a plurality of dies attaching to first side of an interposer with a die formed thereon'20169,397,056'Semiconductor device having trench adjacent to receiving area and method of forming the same'20169,397,060'Package on package structure'20169,397,137'Interconnect structure for CIS flip-chip bonding and methods for forming the same'20169,368,460'Fan-out interconnect structure and method for forming same'20169,362,236'Package structures and methods for forming the same'20169,355,978'Packaging devices and methods of manufacture thereof'20169,343,433'Packages with stacked dies and methods of forming the same'20169,337,135'Pop joint through interposer'20169,331,023'Device packaging'20169,324,587'Method for manufacturing semiconductor structure'20169,305,877'3D package with through substrate vias'20169,305,890'Package having substrate with embedded metal trace overlapped by landing pad'20169,287,143'Apparatus for package reinforcement using molding underfill'20169,275,925'System and method for an improved interconnect structure'20169,263,839'System and method for an improved fine pitch joint'20169,240,387'Wafer-level chip scale package with re-workable underfill'20169,219,030'Package on package structures and methods for forming the same'20159,219,106'Integrated inductor'20159,171,790'Package on package devices and methods of packaging semiconductor dies'20159,165,875'Low profile interposer with stud structure'20159,123,601'Package on package structure'20159,123,763'Package-on-package (PoP) structure having at least one package comprising one die being disposed in a core material between first and second surfaces of the core material'20159,093,411'Pad structure having contact bars extending into substrate and wafer having the pad structure'20159,082,636'Packaging methods and structures for semiconductor devices'20159,041,215'Single mask package apparatus and method'20159,021,682'Apparatus for stud bump formation'20159,013,038'Semiconductor device with post-passivation interconnect structure and method of forming the same'20159,006,891'Method of making a semiconductor device having a post-passivation interconnect structure'20158,987,915'Semiconductor structure and manufacturing method thereof'20158,981,576'Structure and method for bump to landing trace ratio'20158,970,001'Guard ring design for maintaining signal integrity'20158,963,328'Reducing delamination between an underfill and a buffer layer in a bond structure'20158,936,730'Methods for forming apparatus for stud bump formation'20158,916,956'Multiple die packaging interposer structure and method'20148,912,651'Package-on-package (PoP) structure including stud bulbs and method'20148,890,274'Interconnect structure for CIS flip-chip bonding and methods for forming the same'20148,884,412'Multiple die packaging interposer structure and method'20148,884,431'Packaging methods and structures for semiconductor devices'20148,823,180'Package on package devices and methods of packaging semiconductor dies'20148,796,132'System and method for forming uniform rigid interconnect structures'20148,759,964'Wafer level package structure and fabrication methods'20148,749,043'Package on package structure'20148,748,306'Cleaning residual molding compound on solder bumps'20148,735,273'Forming wafer-level chip scale package structures with reduced number of seed layers'20148,716,858'Bump structure with barrier layer on post-passivation interconnect'20148,703,539'Multiple die packaging interposer structure and method'20148,685,798'Methods for forming through vias'20148,669,651'Package-on-package structures with reduced bump bridging'20148,664,041'Method for designing a package and substrate layout'20148,642,393'Package on package devices and methods of forming same'20148,643,196'Structure and method for bump to landing trace ratio'20148,618,827'Measurement of electrical and mechanical characteristics of low-K dielectric in a semiconductor device'20138,610,267'Reducing delamination between an underfill and a buffer layer in a bond structure'20138,581,400'Post-passivation interconnect structure'20138,551,813'Wafer level IC assembly method'20138,540,136'Methods for stud bump formation and apparatus for performing the same'20138,524,595'Semiconductor package structures'20138,501,613'UBM etching methods for eliminating undercut'20138,476,770'Apparatus and methods for forming through vias'20138,409,881'Multi-project wafer and method of making same'20138,377,816'Method of forming electrical connections'20138,334,170'Method for stacking devices'20128,247,267'Wafer level IC assembly method'20128,169,076'Interconnect structures having lead-free solder bumps'20128,049,323'Chip holder with wafer level redistribution layer'20118,039,315'Thermally enhanced wafer level package'20117,952,167'Scribe line layout design'20117,851,272'Multi-project wafer and method of making same'20107,851,331'Bonding structures and methods of forming bonding structures'20107,846,769'Stratified underfill method for an IC package'20107,842,548'Fixture for P-through silicon via assembly'20107,772,691'Thermally enhanced wafer level package'20107,662,665'Method for fabricating a semiconductor package including stress relieving layer for flip chip packaging'20107,656,042'Stratified underfill in an IC package'20107,642,631'Packaged semiconductor chip comprising an integrated circuit chip ablated with laser and cut with saw blade from wafer'20107,588,963'Method of forming overhang support for a stacked semiconductor device'20097,573,138'Stress decoupling structures for flip-chip assembly'20097,491,624'Method of manufacturing low CTE substrates for use with low-k flip-chip package devices'20097,361,990'Reducing cracking of high-lead or lead-free bumps by matching sizes of contact pads and bump pads'20087,265,034'Method of cutting integrated circuit chips from wafer by ablating with laser and cutting with saw blade'20077,170,159'Low CTE substrates for use with low-k flip-chip package devices'20077,116,002'Overhang support for a stacked semiconductor device, and method of forming thereof'20066,600,233'Integrated circuit package with surface mounted pins on an organic substrate'20036,413,849'Integrated circuit package with surface mounted pins on an organic substrate and method of fabrication therefor'20026,191,475'Substrate for reducing electromagnetic interference and enclosure'20016,163,065'Energy-absorbing stable guard ring'20005,936,838'MPC module with exposed C4 die and removal thermal plate design'19995,936,304'C4 package die backside coating'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2003Based in Chandler, AZ, US· patent location history
2006–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (79)· patent assignee history
2006–2019Based in Hsinchu, TW· patent location history
2009–2021Based in Hsinchu County, TW· patent location history
2010–2021Based in Jhudong Township, TW· patent location history
2010–2014Based in Sinpu, TW· patent location history
2012–2017Patents assigned to LII MIRNG-JI (39)· patent assignee history
2012–2017Patents assigned to YU CHEN-HUA (28)· patent assignee history
2013–2017Patents assigned to LIU CHUNG-SHI (13)· patent assignee history
2015–2021Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (80)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 80 | 2015–2021 |
| TAIWAN SEMICONDUCTOR MFG | 79 | 2006–2016 |
| LII MIRNG-JIself | 39 | 2012–2017 |
| YU CHEN-HUA | 28 | 2012–2017 |
| LIU CHUNG-SHI | 13 | 2013–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| Jhudong Township, TW | 110 | 2010–2021 |
| Hsinchu County, TW | 28 | 2009–2021 |
| Hsinchu, TW | 13 | 2006–2019 |
| Chandler, AZ, US | 6 | 1999–2003 |
| Sinpu, TW | 4 | 2010–2014 |