LexDanaLexDanabeta
Inventor

Shreesh Narasimha

Inventor
Beacon, NY, US

Overview

116→
Patents
2004–2021
Patent span
Electricity
Primary field (CPC H)

Patents· 116 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices39%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1021%
H01LSemiconductor devices18%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%
B82YSpecific uses or applications of nanostructures4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G06FElectric digital data processing2%
H10BElectronic memory devices1%
C23CCoating metallic material0%
G11CStatic stores0%
PatentTitleYear
11,101,357Asymmetric high-k dielectric for reducing gate induced drain leakage202111,056,398Forming interconnect without gate cut isolation blocking opening formation202110,833,160Field-effect transistors with self-aligned and non-self-aligned contact openings202010,734,492Asymmetric high-k dielectric for reducing gate induced drain leakage202010,580,686Semiconductor structure with integrated passive structures202010,381,452Asymmetric high-k dielectric for reducing gate induced drain leakage201910,374,048Asymmetric high-k dielectric for reducing gate induced drain leakage201910,367,072Asymmetric high-k dielectric for reducing gate induced drain leakage201910,242,906Semiconductor structure with integrated passive structures201910,083,878Fin fabrication process with dual shallow trench isolation and tunable inner and outer fin profile201810,074,571Device with decreased pitch contact to active regions201810,032,862Semiconductor structure with integrated passive structures20189,922,831'Asymmetric high-k dielectric for reducing gate induced drain leakage'20189,859,122'Asymmetric high-k dielectric for reducing gate induced drain leakage'20189,837,319Asymmetric high-K dielectric for reducing gate induced drain leakage20179,812,396'Interconnect structure for semiconductor devices with multiple power rails and redundancy'20179,812,324'Methods to control fin tip placement'20179,786,545'Method of forming ANA regions in an integrated circuit'20179,768,071'Asymmetric high-K dielectric for reducing gate induced drain leakage'20179,768,195'Semiconductor structure with integrated passive structures'20179,721,843'Asymmetric high-k dielectric for reducing gate induced drain leakage'20179,698,159'Semiconductor structure with integrated passive structures'20179,685,379'Asymmetric high-k dielectric for reducing gate induced drain leakage'20179,659,961'Semiconductor structure with integrated passive structures'20179,577,061'Asymmetric high-K dielectric for reducing gate induced drain leakage'20179,570,354'Asymmetric high-K dielectric for reducing gate induced drain leakage'20179,559,010'Asymmetric high-k dielectric for reducing gate induced drain leakage'20179,543,213'Asymmetric high-k dielectric for reducing gate induced drain leakage'20179,443,929'Shallow trench isolation structure having a nitride plug'20169,437,496'Merged source drain epitaxy'20169,425,079'Semiconductor structure with integrated passive structures'20169,412,667'Asymmetric high-k dielectric for reducing gate induced drain leakage'20169,401,325'Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication'20169,287,399'Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels'20169,269,786'Silicon nitride layer deposited at low temperature to prevent gate dielectric regrowth high-K metal gate field effect transistors'20169,252,146'Work function adjustment by carbon implant in semiconductor devices including gate structure'20169,240,482'Asymmetric stressor DRAM'20169,219,059'Semiconductor structure with integrated passive structures'20159,184,301'Planar and nanowire field effect transistors'20159,136,321'Low energy ion implantation of a junction butting region'20159,105,718'Butted SOI junction isolation structures and devices and method of fabrication'20159,082,877'Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor'20159,064,972'Method of forming a gated diode structure for eliminating RIE damage from cap removal'20159,040,399'Threshold voltage adjustment for thin body MOSFETs'20158,952,460'Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices'20158,940,595'Faceted intrinsic epitaxial buffer layer for reducing short channel effects while maximizing channel stress levels'20158,916,950'Shallow trench isolation structure having a nitride plug'20148,835,231'Methods of forming contacts for nanowire field effect transistors'20148,836,048'Field effect transistor device having a hybrid metal gate stack'20148,829,616'Method and structure for body contacted FET with reduced body resistance and source to drain contact leakage'20148,816,473'Planar polysilicon regions for precision resistors and electrical fuses and method of fabrication'20148,809,152'Germanium oxide free atomic layer deposition of silicon oxide and high-k gate dielectric on germanium containing channel for CMOS devices'20148,803,243'Complementary metal oxide semiconductor (CMOS) device having gate structures connected by a metal gate conductor'20148,779,551'Gated diode structure for eliminating RIE damage from cap removal'20148,741,725'Butted SOI junction isolation structures and devices and method of fabrication'20148,729,637'Work function adjustment by carbon implant in semiconductor devices including gate structure'20148,698,128'Gate-all around semiconductor nanowire FET\'s on bulk semicoductor wafers'20148,680,617'Split level shallow trench isolation for area efficient body contacts in SOI MOSFETS'20148,674,342'Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers'20148,592,295'Gate-all around semiconductor nanowire FETs on bulk semiconductor wafers'20138,586,966'Contacts for nanowire field effect transistors'20138,558,313'Bulk substrate FET integrated on CMOS SOI'20138,541,295'Pad-less gate-all around semiconductor nanowire FETs on bulk semiconductor wafers'20138,536,563'Nanowire field effect transistors'20138,513,068'Nanowire field effect transistors'20138,490,029'Method of fabricating a device using low temperature anneal processes, a device and design structure'20138,455,334'Planar and nanowire field effect transistors'20138,343,825'Reducing dislocation formation in semiconductor devices through targeted carbon implantation'20138,343,781'Electrical mask inspection'20138,302,040'Compact model methodology for PC landing pad lithographic rounding impact on device performance'20128,296,691'Methodology for improving device performance prediction from effects of active area corner rounding'20128,236,709'Method of fabricating a device using low temperature anneal processes, a device and design structure'20128,232,599'Bulk substrate FET integrated on CMOS SOI'20128,232,603'Gated diode structure and method including relaxed liner'20128,097,515'Self-aligned contacts for nanowire field effect transistors'20128,053,325'Body contact structures and methods of manufacturing the same'20118,017,483'Method of creating asymmetric field-effect-transistors'20117,993,990'Multiple crystallographic orientation semiconductor structures'20117,979,815'Compact model methodology for PC landing pad lithographic rounding impact on device performance'20117,956,415'SOI transistor having a carrier recombination structure in a body'20117,932,144'Semiconductor structure and method of forming the structure'20117,928,571'Device having dual etch stop liner and reformed silicide layer and related methods'20117,893,494'Method and structure for SOI body contact FET with reduced parasitic capacitance'20117,859,061'Halo-first ultra-thin SOI FET for superior short channel control'20107,818,693'Methodology for improving device performance prediction from effects of active area corner rounding'20107,814,454'Selectable device options for characterizing semiconductor devices'20107,804,140'Field effect transistor with reduced shallow trench isolation induced leakage current'20107,776,695'Semiconductor device structure having low and high performance devices of same conductive type on same substrate'20107,767,579'Protection of SiGe during etch and clean operations'20107,732,270'Device having enhanced stress state and related methods'20107,714,358'Semiconductor structure and method of forming the structure'20107,713,807'High-performance CMOS SOI devices on hybrid crystal-oriented substrates'20107,709,910'Semiconductor structure for low parasitic gate capacitance'20107,696,573'Multiple crystallographic orientation semiconductor structures'20107,687,338'Method of reducing embedded SiGe loss in semiconductor device manufacturing'20107,627,836'OPC trimming for performance'20097,595,247'Halo-first ultra-thin SOI FET for superior short channel control'20097,550,337'Dual gate dielectric SRAM'20097,538,391'Curved FINFETs'20097,518,145'Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same'20097,462,916'Semiconductor devices having torsional stresses'20087,456,115'Method for forming semiconductor devices having reduced gate edge leakage current'20087,446,062'Device having dual etch stop liner and reformed silicide layer and related methods'20087,446,395'Device having dual etch stop liner and protective layer'20087,348,635'Device having enhanced stress state and related methods'20087,329,923'High-performance CMOS devices on hybrid crystal oriented substrates'20087,306,983'Method for forming dual etch stop liner and protective layer in a semiconductor device'20077,274,072'Hybrid bulk-SOI 6T-SRAM cell for improved cell stability and performance'20077,227,204'Structure for improved diode ideality'20077,202,187'Method of forming sidewall spacer using dual-frequency plasma enhanced CVD'20077,189,644'CMOS device integration for low external resistance'20077,091,128'Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs'20067,071,072'Forming shallow trench isolation without the use of CMP'20067,001,844'Material for contact etch layer to enhance device performance'20066,991,979'Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs'20066,825,102'Method of improving the quality of defective semiconductor material'2004

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2004–2020Patents assigned to IBM (102)· patent assignee history
2004–2021Based in Beacon, NY, US· patent location history
2011–2014Based in Hopewell Junction, NY, US· patent location history
2012–2015Patents assigned to NARASIMHA SHREESH (27)· patent assignee history
2012–2015Patents assigned to SLEIGHT JEFFREY W (9)· patent assignee history
2012–2015Patents assigned to BANGSARUNTIP SARUNYA (7)· patent assignee history
2012–2015Based in Yorktown Heights, NY, US· patent location history
2015–2020Patents assigned to GLOBALFOUNDRIES INC (10)· patent assignee history
2020Based in Charlotte, NC, US· patent location history
2021Based in Clifton Park, NY, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM1022004–2020
NARASIMHA SHREESHself272012–2015
GLOBALFOUNDRIES INC102015–2020
SLEIGHT JEFFREY W92012–2015
BANGSARUNTIP SARUNYA72012–2015
Locations
LocationPatentsSpan
Beacon, New York, US1042004–2021
Hopewell Junction, New York, US62011–2014
Yorktown Heights, New York, US32012–2015
Clifton Park, New York, US12021
Charlotte, NC, US12020