Methodology for improving device performance prediction from effects of active area corner rounding

A method for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device, said transistor including an active device (RX) area over which said gate is formed and over which said conductive line feature extends, the method comprising:nproviding, to a processor device, an analytical model representation for said transistor device structure, said analytical model representation including a function for modeling a lithographic corner rounding flare effect impacting an active device area width,performing an extraction to determine a distance between an edge of said conductive line feature and an RX edge portion;determining, from said modeling function, an effective change in active device area width (deltaW adder) as a function of said distance; andupdating, by said processor device, transistor model parameter values in a transistor compact model for said transistor device to include deltaW adder values to be added to a built-in deltaW value, wherein a netlist used in a simulation includes the deltaW adder values to describe the characteristics of the transistor device to thereby model lithographic corner rounding effect of said active device area on transistor device parametrics.

A system for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device, said transistor including an active device (RX) area over which said gate is formed and over which said conductive line feature extends, the system comprising:na memory;a processor device in communications with the memory, wherein the system performs a method comprising:nproviding, to said processor device, an analytical model representation for said transistor device structure, said analytical model representation including a function for modeling a lithographic corner rounding flare effect impacting an active device area width,performing an extraction to determine a distance between an edge of said conductive line feature and an RX edge portion formed as a result of said lithographic flare effect of said active device area;determining, from said modeling function, an effective change in active device area width (deltaW adder) as a function of said distance; andupdating, by said processor device, transistor model parameter values in a transistor compact model for said transistor device to include deltaW adder values to be added to a built-in deltaW value, said memory storing said updated transistor model parameter values;wherein a netlist used in a simulation includes the stored deltaW adder values to describe the characteristics of the transistor device to thereby model lithographic corner rounding effect of said active device area on transistor device parametrics.

A program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine to perform method steps for modeling a semiconductor transistor device structure having a conductive line feature of a designed length connected to a gate of a transistor device in a circuit to be modeled, said transistor including an active device (RX) area over which said gate is formed and over which said conductive line feature extends, the method comprising the steps of:nproviding, to a processor device, an analytical model representation for said transistor device structure, said analytical model representation including a function for modeling a lithographic corner rounding flare effect impacting an active device area width,performing an extraction to determine a distance between an edge of said conductive line feature and an RX edge portion formed as a result of said lithographic flare effect;determining, from said modeling function, an effective change in active device area width (deltaW adder) as a function of said distance; andupdating, by said processor device, transistor model parameter values in a transistor compact model for said transistor device to include deltaW adder values to be added to a built-in deltaW value, wherein a netlist used in a simulation includes the deltaW adder values to describe the characteristics of the transistor device to thereby model lithographic corner rounding effect of said active device area on transistor device parametrics.