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Inventor

Sudhir K. Madan

Inventor
Richardson, TX, US

Overview

48→
Patents
1989–2018
Patent span
Physics
Primary field (CPC G)

Patents· 48 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores40%
H10BElectronic memory devices16%
H10DInorganic electric semiconductor devices15%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests11%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G06FElectric digital data processing4%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h104%
H03KPulse technique1%
Y10TTechnical subjects covered by former us classification1%
PatentTitleYear
9,972,364Method to maintain power supply voltage during brownout20189,117,535'Single sided bit line restore for power reduction'20158,811,057'Power reduction circuit and method'20148,570,812'Method of reading a ferroelectric memory cell'20138,423,837'High reliability and low power redundancy for memory'20138,381,075'Low-power redundancy for non-volatile memory'20138,296,628'Data path read/write sequencing for reduced power consumption'20128,154,938'Memory array power domain partitioning'20127,920,404'Ferroelectric memory devices with partitioned platelines'20117,804,702'Ferroelectric memory cell with access transmission gate'20107,733,682'Plateline driver for a ferroelectric memory'20107,630,257'Methods and systems for accessing memory'20097,561,458'Ferroelectric memory array for implementing a zero cancellation scheme to reduce plateline voltage in ferroelectric memory'20097,463,504'Active float for the dummy bit lines in FeRAM'20087,443,708'Low resistance plate line bus architecture'20087,349,237'Plateline driver with RAMP rate control'20087,301,795'Accelerated low power fatigue testing of FRAM'20077,244,995'Scrambling method to reduce wordline coupling noise'20077,230,868'Stable source-coupled sense amplifier'20077,200,027'Ferroelectric memory reference generator systems using staging capacitors'20077,193,880'Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory'20077,133,304'Method and apparatus to reduce storage node disturbance in ferroelectric memory'20067,087,493'Memory with 6T small aspect ratio cells having metal—1 elements physically connected to metal—0 elements'20067,009,864'Zero cancellation scheme to reduce plateline voltage in ferroelectric memory'20066,906,945'Bitline precharge timing scheme to improve signal margin'20056,856,535'Reference voltage generator for ferroelectric memory'20056,809,954'Circuit and method for reducing access transistor gate oxide stress'20046,768,144'Method and apparatus for reducing leakage current in an SRAM array'20046,757,206'Sense amplifier with override write circuitry'20046,721,217'Method for memory sensing'20046,593,630'Memory cell with reduced coupling between pass transistor and drive transistor bodies and method'20036,414,359'Six transistor SRAM cell having offset p-channel and n-channel transistors'20026,285,088'Compact memory circuit'20016,141,240'Apparatus and method for static random access memory array'20006,091,626'Low voltage, low power static random access memory cell'20005,952,688'Stacked DRAM structure'19995,828,597'Low voltage, low power static random access memory cell'19985,712,182'Method of forming a microelectronic device having a cavity smaller than lithographic tolerances'19985,629,228'Method of making stacked DRAM capacitor structure by using a conformal conductor'19975,604,659'Microelectronic device with centered storage capacitor cavity sized less than feature size'19975,539,612'Intermediate structure for forming a storage capacitor'19965,468,676'Trench isolation structure and method for forming'19955,350,941'Trench isolation structure having a trench formed in a LOCOS structure and a channel stop region on the sidewalls of the trench'19945,341,272'Increased capacitance memory cell capacitor'19945,114,879'Method of forming a microelectronic contact'19924,994,873'Local interconnect for stacked polysilicon device'19914,921,813'Method for making a polysilicon transistor'19904,829,024'Method of forming layered polysilicon filled contact by doping sensitive endpoint etching'1989

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1989–1991Patents assigned to MOTOROLA INC (3)· patent assignee history
1989–1990Based in Austin, TX, US· patent location history
1991–2001Based in Dallas, TX, US· patent location history
1992–2018Patents assigned to TEXAS INSTRUMENTS INC (44)· patent assignee history
1998–2018Based in Richardson, TX, US· patent location history
2004Patents assigned to AGILENT TECHNOLOGIES INC (1)· patent assignee history
2012–2018Patents assigned to MADAN SUDHIR K (6)· patent assignee history
2013Patents assigned to TOOPS DAVID J (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC441992–2018
MADAN SUDHIR Kself62012–2018
MOTOROLA INC31989–1991
TOOPS DAVID J22013
AGILENT TECHNOLOGIES INC12004
Locations
LocationPatentsSpan
Richardson, Texas, US341998–2018
Dallas, Texas, US121991–2001
Austin, Texas, US21989–1990