Increased capacitance memory cell capacitor

A method of forming a microelectronic device, said method comprising the steps of: a) providing a substrate; b) forming a conductive region at said substrate; c) forming an insulating layer on said conductive region and said substrate; d) removing selective portions of said insulating layer to expose a selective area of said conductive region thereby forming a storage node contact window; e) forming a first conductive layer on said insulating layer and within said storage node contact window wherein said first conductive layer is in electrical communication with said conductive region; f) forming a cavity in said first conductive layer; g) removing selective portions of the said first conductive layer leaving at least a remaining portion of said first conductive layer in which said cavity was formed, thereby isolating said remaining portion of said first conductive layer from surrounding circuit elements to form a storage electrode which lies above the plane of the substrate and has exposed sidewalls; h) forming a dielectric layer over said storage electrode including said sidewalls; and i) forming a second conductive layer over said dielectric layer to act as a plate electrode capacitively-coupled to said storage electrode through said dielectric layer whereby an increased capacitance memory cell capacitor is formed having a plate area equal to the surface area of the storage electrode including the cavity and the sidewalls.

A method of forming a microelectronic device, said method comprising the steps of: a) providing a substrate; b) adding impurities to a selected region of said substrate to a conductive region therein; c) depositing an insulating glass layer on said conductive region and said substrate; d) removing area of said conductive region thereby forming a storage node contact window; e) depositing a first highly doped polysilicon layer on said insulating layer and within said storage node contact window wherein said first polysilicon layer is in electrical communication with said conductive region; f) forming a cavity in said first polysilicon layer; g) removing selective portions of the said first conductive layer leaving at least a remaining portion of said first conductive layer in which said cavity was formed, thereby isolating said remaining portion of said first conductive layer from surrounding circuit elements to form a storage electrode which lies above the plane of the substrate and has exposed sidewalls; h) forming a dielectric layer over said storage electrode including said sidewalls; and i) forming a second highly doped polysilicon layer over said dielectric layer to act as a plate electrode capacitively-coupled to said storage electrode through said dielectric layer whereby an increased capacitance memory cell capacitor is formed having a plate area equal to the surface area of the storage electrode including the cavity and the sidewalls.

A microelectronic device, said microelectronic device comprising: a) a substrate including a conductive region; b) an insulating layer overlying said substrate having a storage node contact window overlying a selected area of said conductive region; c) a storage electrode into which a cavity has been defined and which is in electrical communication with said conductive region of said substrate and having sidewalls extending a selected distance above said insulating layer; d) a dielectric layer conformably covering said storage electrode including said sidewalls; and e) a conductive layer covering said dielectric layer and forming a plate electrode capacitively-coupled to said storage electrode whereby an increased capacitance memory cell capacitor is formed having a plate area equal to the surface area of the storage electrode including the cavity and the sidewalls.