Inventor

Dominic J. Schepis

Inventor

Wappingers Falls, NY, US

Overview

1985–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 141 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices33%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1024%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1018%

H01LSemiconductor devices16%

H10BElectronic memory devices3%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

G06FElectric digital data processing1%

H01HElectric switches1%

H10NElectric solid-state devices not otherwise provided for1%

B82YSpecific uses or applications of nanostructures0%

PatentTitleYear

10,680,085Transistor structure with varied gate cross-sectional area2020 10,658,494Transistors and methods of forming transistors using vertical nanowires2020 10,643,907Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step2020 10,453,959Fin replacement in a field-effect transistor2019 10,438,858Low-cost SOI FinFET technology2019 10,211,320Fin cut without residual fin defects2019 10,204,837Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step2019 10,199,220Semiconductor structure having insulator pillars and semiconductor material on substrate2019 10,177,168Fin field-effect transistor having an oxide layer under one or more of the plurality of fins2019 10,170,304Self-aligned nanotube structures2019 10,032,870Low defect III-V semiconductor template on porous silicon2018 10,014,322Local SOI fins with multiple heights2018 10,002,948FinFET having highly doped source and drain regions2018 10,002,798Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step2018 9,972,620Preventing shorting between source and/or drain contacts and gate2018 9,966,457Transistor structure with varied gate cross-sectional area2018 9,935,181FinFET having highly doped source and drain regions2018 9,899,274'Low-cost SOI FinFET technology'2018 9,875,939Methods of forming uniform and pitch independent fin recess2018 9,812,575'Contact formation for stacked FinFETs'2017 9,793,113'Semiconductor structure having insulator pillars and semiconductor material on substrate'2017 9,754,941'Method and structure to form tensile strained SiGe fins and compressive strained SiGe fins on a same substrate'2017 9,735,257'finFET having highly doped source and drain regions'2017 9,728,626'Almost defect-free active channel region'2017 9,722,052'Fin cut without residual fin defects'2017 9,679,763'Silicon-on-insulator fin field-effect transistor device formed on a bulk substrate'2017 9,673,108'Fabrication of higher-K dielectrics'2017 9,660,059'Fin replacement in a field-effect transistor'2017 9,647,119'Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step'2017 9,634,142'Method for improving boron diffusion in a germanium-rich fin through germanium concentration reduction in fin S/D regions by thermal mixing'2017 9,601,624'SOI based FINFET with strained source-drain regions'2017 9,590,077'Local SOI fins with multiple heights'2017 9,525,027'Lateral bipolar junction transistor having graded SiGe base'2016 9,514,995'Implant-free punch through doping layer formation for bulk FinFET structures'2016 9,478,425'Fabrication of higher-k dielectrics'2016 9,478,642'Semiconductor junction formation'2016 9,472,460'Uniform depth fin trench formation'2016 9,472,470'Methods of forming FinFET with wide unmerged source drain EPI'2016 9,466,602'Embedded dynamic random access memory field effect transistor device'2016 9,461,052'Embedded dynamic random access memory field effect transistor device'2016 9,455,141'Silicon-germanium fin of height above critical thickness'2016 9,450,079'FinFET having highly doped source and drain regions'2016 9,443,873'Structure and method for tensile and compressive strained silicon germanium with same germanium concentration by single epitaxy step'2016 9,391,198'Strained semiconductor trampoline'2016 9,390,925'Siliconâ€”germanium (SiGe) fin formation'2016 9,385,023'Method and structure to make fins with different fin heights and no topography'2016 9,368,492'Forming fins of different materials on the same substrate'2016 9,368,512'Double diamond shaped unmerged epitaxy for tall fins in tight pitch'2016 9,343,550'Silicon-on-nothing FinFETs'2016 9,305,883'Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings'2016 9,236,397'FinFET device containing a composite spacer structure'2016 9,224,811'Stacked semiconductor device'2015 9,123,826'Single crystal source-drain merged by polycrystalline material'2015 9,041,062'Silicon-on-nothing FinFETs'2015 8,999,779'Locally raised epitaxy for improved contact by local silicon capping during trench silicide processings'2015 8,963,283'Method of fabricating isolated capacitors and structure thereof'2015 8,940,617'Method of fabricating isolated capacitors and structure thereof'2015 8,716,776'Method of fabricating isolated capacitors and structure thereof'2014 8,685,806'Silicon-on-insulator substrate with built-in substrate junction'2014 8,685,845'Epitaxial growth of silicon doped with carbon and phosphorus using hydrogen carrier gas'2014 8,652,925'Method of fabricating isolated capacitors and structure thereof'2014 8,643,061'Structure of high-K metal gate semiconductor transistor'2014 8,575,655'Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering'2013 8,482,009'Silicon-on-insulator substrate with built-in substrate junction'2013 8,440,547'Method and structure for PMOS devices with high K metal gate integration and SiGe channel engineering'2013 8,389,352'Silicon germanium film formation method and structure'2013 8,361,859'Stressed transistor with improved metastability'2013 8,354,314'Silicon germanium film formation method and structure'2013 8,232,186'Methods of integrating reverse eSiGe on NFET and SiGe channel on PFET, and related structure'2012 8,173,524'Process for epitaxially growing epitaxial material regions'2012 8,128,749'Fabrication of SOI with gettering layer'2012 7,955,950'Semiconductor-on-insulator substrate with a diffusion barrier'2011 7,955,940'Silicon-on-insulator substrate with built-in substrate junction'2011 7,781,800'Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer'2010 7,781,273'Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure'2010 7,759,213'Pattern independent Si:C selective epitaxy'2010 7,682,915'Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance'2010 7,622,341'Sige channel epitaxial development for high-k PFET manufacturability'2009 7,544,994'Semiconductor structure with multiple fins having different channel region heights and method of forming the semiconductor structure'2009 7,446,005'Manufacturable recessed strained RSD structure and process for advanced CMOS'2008 7,446,350'Embedded silicon germanium using a double buried oxide silicon-on-insulator wafer'2008 7,381,623'Pre-epitaxial disposable spacer integration scheme with very low temperature selective epitaxy for enhanced device performance'2008 RE040339'Silicon-on-insulator chip having an isolation barrier for reliability'2008 7,348,633'Hybrid crystallographic surface orientation substrate having one or more SOI regions and/or bulk semiconductor regions'2008 7,183,573'Disposable spacer for symmetric and asymmetric Schottky contact to SOI mosfet'2007 7,166,521'SOI wafers with 30-100 â„« buried oxide (BOX) created by wafer bonding using 30-100 â„« thin oxide as bonding layer'2007 7,163,866'SOI MOSFETS exhibiting reduced floating-body effects'2007 7,115,955'Semiconductor device having a strained raised source/drain'2006 7,115,463'Patterning SOI with silicon mask to create box at different depths'2006 6,900,092'Surface engineering to prevent epi growth on gate poly during selective epi processing'2005 6,891,228'CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture'2005 6,884,667'Field effect transistor with stressed channel and method for making same'2005 6,835,633'SOI wafers with 30-100 buried oxide (BOX) created by wafer bonding using 30-100 thin oxide as bonding layer'2004 6,828,630'CMOS device on ultrathin SOI with a deposited raised source/drain, and a method of manufacture'2004 6,808,974'CMOS structure with maximized polysilicon gate activation and a method for selectively maximizing doping activation in gate, extension, and source/drain regions'2004 6,717,216'SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device'2004 6,686,629'SOI MOSFETS exhibiting reduced floating-body effects'2004 6,645,795'Polysilicon doped transistor using silicon-on-insulator and double silicon-on-insulator'2003 6,602,759'Shallow trench isolation for thin silicon/silicon-on-insulator substrates by utilizing polysilicon'2003 6,599,813'Method of forming shallow trench isolation for thin silicon-on-insulator substrates'2003 6,563,173'Silicon-on-insulator chip having an isolation barrier for reliability'2003 6,541,317'Polysilicon doped transistor'2003 6,531,375'Method of forming a body contact using BOX modification'2003 6,521,947'Method of integrating substrate contact on SOI wafers with STI process'2003 6,506,649'Method for forming notch gate having self-aligned raised source/drain structure'2003 6,492,684'Silicon-on-insulator chip having an isolation barrier for reliability'2002 6,451,634'Method of fabricating a multistack 3-dimensional high density semiconductor device'2002 6,440,807'Surface engineering to prevent EPI growth on gate poly during selective EPI processing'2002 6,437,377'Low dielectric constant sidewall spacer using notch gate process'2002 6,429,488'Densely patterned silicon-on-insulator (SOI) region on a wafer'2002 6,429,084'MOS transistors with raised sources and drains'2002 6,404,014'Planar and densely patterned silicon-on-insulator structure'2002 6,395,587'Fully amorphized source/drain for leaky junctions'2002 6,387,742'Thermal conductivity enhanced semiconductor structures and fabrication processes'2002 6,352,905'Method and structure of high and low K buried oxide for SOI technology'2002 6,339,005'Disposable spacer for symmetric and asymmetric Schottky contact to SOI MOSFET'2002 6,291,858'Multistack 3-dimensional high density semiconductor device and method for fabrication'2001 6,288,426'Thermal conductivity enhanced semiconductor structures and fabrication processes'2001 6,281,095'Process of manufacturing silicon-on-insulator chip having an isolation barrier for reliability'2001 6,255,145'Process for manufacturing patterned silicon-on-insulator layers with self-aligned trenches and resulting product'2001 6,214,694'Process of making densely patterned silicon-on-insulator (SOI) region on a wafer'2001 6,180,486'Process of fabricating planar and densely patterned silicon-on-insulator structure'2001 6,166,420'Method and structure of high and low K buried oxide for SoI technology'2000 6,133,610'Silicon-on-insulator chip having an isolation barrier for reliability and process of manufacture'2000 5,811,357'Process of etching an oxide layer'1998 5,646,053'Method and structure for front-side gettering of silicon-on-insulator substrates'1997 5,622,892'Method of making a self cooling electrically programmable fuse'1997 5,614,440'Method of forming a thermally activated noise immune fuse'1997 5,585,663'Self cooling electrically programmable fuse'1996 5,504,434'Instrument for the measurement of electrical characteristics during manufacturing processes'1996 5,485,032'Antifuse element with electrical or optical programming'1996 5,444,287'Thermally activated noise immune fuse'1995 5,394,294'Self protective decoupling capacitor structure'1995 5,314,840'Method for forming an antifuse element with electrical or optical programming'1994 5,298,784'Electrically programmable antifuse using metal penetration of a junction'1994 5,279,987'Fabricating planar complementary patterned subcollectors with silicon epitaxial layer'1994 5,086,016'Method of making semiconductor device contact including transition metal-compound dopant source'1992 4,960,726'BiCMOS process'1990 4,758,531'Method of making defect free silicon islands using SEG'1988 4,661,832'Total dielectric isolation for integrated circuits'1987 4,502,913'Total dielectric isolation for integrated circuits'1985

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1985–2020Patents assigned to IBM (113)· patent assignee history

1985–2020Based in Wappingers Falls, NY, US· patent location history

2002–2020Based in Wappinger Falls, NY, US· patent location history

2011–2014Based in Hopewell Junction, NY, US· patent location history

2012–2014Patents assigned to SCHEPIS DOMINIC J (11)· patent assignee history

2012–2014Patents assigned to CHAKRAVARTI ASHIMA B (5)· patent assignee history

2012–2014Patents assigned to DUBE ABHISHEK (4)· patent assignee history

2015–2020Patents assigned to GLOBALFOUNDRIES INC (28)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	113	1985–2020
GLOBALFOUNDRIES INC	28	2015–2020
SCHEPIS DOMINIC Jself	11	2012–2014
CHAKRAVARTI ASHIMA B	5	2012–2014
DUBE ABHISHEK	4	2012–2014

Locations

Location	Patents	Span
Wappingers Falls, New York, US	131	1985–2020
Wappinger Falls, New York, US	7	2002–2020
Hopewell Junction, New York, US	3	2011–2014