Inventor

Shekhar Y. Borkar

Inventor

Beaverton, OR, US

Overview

74→

Patents

1988–2018

Patent span

Electricity

Primary field (CPC H)

Patents· 74 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing21%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1010%

H03KPulse technique9%

H04LTransmission of digital information, e.g. telegraphic communication8%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use6%

H10DInorganic electric semiconductor devices5%

G11CStatic stores4%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%

H01GCapacitors3%

H02JElectric power networks3%

PatentTitleYear

10,021,743Light devices having controllable light emitting elements2018 9,992,135Apparatus and method for fusion of compute and switching functions of exascale system into a single component by using configurable network-on-chip fabric with distributed dual mode input-output ports and programmable network interfaces2018 9,837,391Scalable polylithic on-package integratable apparatus and method2017 9,673,637'Ultra-capacitor based energy storage in a battery form factor'2017 9,516,712'Light devices having controllable light emitting elements'2016 8,694,816'Power delivery system in which VRM and CPU exchange power consumption measurements'2014 8,573,807'Light devices having controllable light emitting elements'2013 8,288,846'Power management integrated circuit'2012 8,284,766'Multi-core processor and method of communicating across a die'2012 7,774,590'Resiliently retaining state information of a many-core processor'2010 7,698,576'CPU power delivery system'2010 7,671,456'Power management integrated circuit'2010 7,653,165'Pulse amplitude modulated system with reduced intersymbol interference'2010 7,568,115'Power delivery and power management of many-core processors'2009 7,541,782'System and method for extracting energy from an ultracapacitor'2009 7,523,337'Power delivery system in which power supply and load exchange power consumption measurements via digital bus'2009 7,482,792'IC with fully integrated DC-to-DC power converter'2009 7,412,353'Reliable computing with a many-core processor'2008 7,391,834'Pulse amplitude modulated system with reduced intersymbol interference'2008 7,324,328'Integrated ultracapacitor as energy source'2008 7,247,930'Power management integrated circuit'2007 7,181,544'Network protocol engine'2007 7,177,288'Simultaneous transmission and reception of signals in different frequency bands over a bus line'2007 7,171,510'On-chip observability buffer to observer bus traffic'2007 7,169,631'Silicon and silicon/germanium light-emitting device, methods and systems'2007 7,167,015'Active cooling to reduce leakage power'2007 7,080,111'Floating point multiply accumulator'2006 7,050,291'Integrated ultracapacitor as energy source'2006 7,016,354'Packet-based clock signal'2006 6,924,510'Silicon and silicon/germanium light-emitting device, methods and systems'2005 6,894,536'Low power NRZ interconnect for pulsed signaling'2005 6,847,617'Systems for interchip communication'2005 6,845,424'Memory pass-band signaling'2005 6,809,538'Active cooling to reduce leakage power'2004 6,747,474'Integrated circuit stubs in a point-to-point system'2004 6,741,107'Synchronous clock generator for integrated circuits'2004 6,593,799'Circuit including forward body bias from supply voltage and ground nodes'2003 6,538,584'Transition reduction encoder using current and last bit sets'2003 6,536,025'Receiver deskewing of multiple source synchronous bits from a parallel bus'2003 6,484,265'Software control of transistor body bias in controlling chip parameters'2002 6,462,943'Method and apparatus for retrofit mounting a VLSI chip to a computer chassis for current supply'2002 6,441,649'Rail-to-rail input clocked amplifier'2002 6,437,601'Using a timing strobe for synchronization and validation in a digital logic device'2002 6,415,388'Method and apparatus for power throttling in a microprocessor using a closed loop feedback system'2002 6,411,156'Employing transistor body bias in controlling chip parameters'2002 6,380,781'Soft error rate tolerant latch'2002 6,373,289'Data and strobe repeater having a frequency control unit to re-time the data and reject delay variation in the strobe'2002 6,366,156'Forward body bias voltage generation systems'2002 6,330,680'Method and apparatus for power throttling in a microprocessor using a closed loop feedback system'2001 6,300,819'Circuit including forward body bias from supply voltage and ground nodes'2001 6,272,666'Transistor group mismatch detection and reduction'2001 6,266,288'Methods for reducing the effects of power supply distribution related noise'2001 6,232,827'Transistors providing desired threshold voltage and reduced short channel effects with forward body bias'2001 6,218,892'Differential circuits employing forward body bias'2001 6,218,895'Multiple well transistor circuits having forward body bias'2001 6,137,688'Apparatus for retrofit mounting a VLSI chip to a computer chassis for current supply'2000 6,111,804'Methods for reducing the effects of power supply distribution related noise'2000 6,100,751'Forward body biased field effect transistor providing decoupling capacitance'2000 6,072,740'Apparatus for reducing the effects of power supply distribution related noise'2000 6,067,232'System for connecting subsystems of dissimilar thermal properties'2000 6,018,465'Apparatus for mounting a chip package to a chassis of a computer'2000 5,978,228'Apparatus for mounting a very large scale integration (VLSI) chip to a computer chassis for cooling'1999 5,969,944'Method and apparatus for mounting a very large scale integration (VLSI) chip package to a computer chasis for cooling'1999 5,943,270'Two-transistor DRAM cell for logic process technology'1999 5,880,945'Power conversion and load circuit on same integrated circuit'1999 5,634,043'Microprocessor point-to-point communication'1997 5,623,644'Point-to-point phase-tolerant communication'1997 5,604,450'High speed bidirectional signaling scheme'1997 5,546,023'Daisy chained clock distribution scheme'1996 5,063,308'Output driver with static and transient parts'1991 5,047,922'Virtual I/O'1991 4,975,598'Temperature, voltage, and process compensated output driver'1990 4,809,167'Circuitry for emulating single chip microcomputer without access to internal buses'1989 4,782,439'Direct memory access system for microcontroller'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2018Patents assigned to INTEL CORP (72)· patent assignee history

1988–2002Based in Portland, OR, US· patent location history

1989Based in Mesa, AZ, US· patent location history

1999–2018Based in Beaverton, OR, US· patent location history

2012–2017Patents assigned to BORKAR SHEKHAR Y (3)· patent assignee history

2012–2014Patents assigned to BORKAR SHEKHAR (2)· patent assignee history

2012–2014Patents assigned to HAZUCHA PETER (2)· patent assignee history

2012–2014Patents assigned to KARNIK TANAY (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	72	1988–2018
BORKAR SHEKHAR Yself	3	2012–2017
BORKAR SHEKHARself	2	2012–2014
HAZUCHA PETER	2	2012–2014
KARNIK TANAY	2	2012–2014

Locations

Location	Patents	Span
Beaverton, OR, US	59	1999–2018
Portland, OR, US	14	1988–2002
Mesa, AZ, US	1	1989