A semiconductor device having a two-port type static random access memory, one memory cell of which includes first and second inverters, the first inverter comprises first and third transistors and the second inverter comprises second and fourth transistors, comprising: first and second well regions of a first conductivity type; a third well region of a second conductivity type disposed between the first and second well regions in a plane view; a first pair of impurity regions of the first conductivity type provided in the third well region, functioning as two electrodes of the first transistor; a second pair of impurity regions of the first conductivity type provided in the third well region, functioning as two electrodes of the second transistor; a third pair of impurity regions of the second conductivity type provided in the first well region, functioning as two electrodes of the third transistor; a fourth pair of impurity regions of the second conductivity type provided in the first well region, functioning as two electrodes of the fourth transistor; a fifth pair of impurity regions of the second conductivity type provided in the first well region, functioning as two electrodes of a fifth transistor; a sixth pair of impurity regions of the second conductivity type provided in the second well region, functioning as two electrodes of a sixth transistor; a seventh pair of impurity regions of the second conductivity type provided in the second well region, functioning as two electrodes of a seventh transistor; an eighth pair of impurity regions of the second conductivity type provided in the second well region, functioning as two electrodes of an eighth transistor; a first conductive layer provided over the first and third well regions, functioning as a gate electrode common to the first and third transistors; a second conductive layer provided over the second and third well regions, functioning as a gate electrode common to the second and fourth transistors; a third conductive layer provided over the first well region, functioning as a gate electrode common to the fifth and sixth transistors; a fourth conductive layer provided over the second well region, functioning as a gate electrode common to the seventh and eighth transistors; a fifth conductive layer electrically connected to the second conductive layer, one of the first pair of impurity regions, one of the third pair of impurity regions, one of the fifth pair of impurity regions and one of the eighth pair of impurity regions, and functioning as one storage terminal of the one memory cell; a sixth conductive layer electrically connected to the first conductive layer, one of the second pair of impurity regions, one of the fourth pair of impurity regions, one of the seventh pair of impurity regions and one of the sixth pair of impurity regions, and functioning as another storage terminal of the one memory cell; a first word line electrically connected to the third conductive layer; a second word line electrically connected to the fourth conductive layer; a first bit line electrically connected to the other of the fifth pair of impurity regions; a second bit line electrically connected to the other of the sixth pair of impurity regions; a third bit line electrically connected to the other of the seventh pair of impurity regions; and a fourth bit line electrically connected to the other of the eighth pair of impurity regions.
›5.↳ 4The semiconductor device according to claim 4, wherein a first supply voltage is supplied to the other of the first pair of impurity regions and the o…d2
The semiconductor device according to claim 4, wherein a first supply voltage is supplied to the other of the first pair of impurity regions and the other of the second pair of impurity regions, and a second supply voltage is supplied to the other of the third pair of impurity regions and the other of the fourth pair of impurity regions.
›6.↳ 4The semiconductor device according to claim 4, wherein the ones of the third and fifth pairs of impurity regions are a common impurity region, and the…d2
The semiconductor device according to claim 4, wherein the ones of the third and fifth pairs of impurity regions are a common impurity region, and the ones of the fourth and seventh pairs of impurity regions are a common impurity region.
›7.↳ 4The semiconductor device according to claim 4, wherein the one of the first pair of impurity regions is electrically connected to the fifth conductive…d2
The semiconductor device according to claim 4, wherein the one of the first pair of impurity regions is electrically connected to the fifth conductive layer via a first contact hole disposed between overlapped portions of the fifth conductive layer and the one of the first pair of impurity regions in the plane view, the one of the third pair of impurity regions is electrically connected to the fifth conductive layer via a second contact hole disposed between overlapped portions of the fifth conductive layer and the one of the third pair of impurity regions in the plane view, the one of the eighth pair of impurity regions is electrically connected to the fifth conductive layer via a third contact hole disposed between overlapped portions of the fifth conductive layer and the one of the eighth impurity regions in the plane view, the one of the second pair of impurity regions is electrically connected to the sixth conductive layer via a fourth contact hole disposed between overlapped portions of the sixth conductive layer and the one of the second pair of impurity regions in the plane view, the one of the fourth pair of impurity regions is electrically connected to the sixth conductive layer via a fifth contact hole disposed between overlapped portions of the sixth conductive layer and the one of the sixth pair of impurity regions in the plane view, and the one of the sixth pair of impurity regions is electrically connected to the sixth conductive layer via a sixth contact hole disposed between overlapped portions of the sixth conductive layer and the one of the fifth pair of impurity regions in the plane view.
›8.↳ 4The semiconductor device according to claim 4, wherein the second conductive layer is electrically connected to the fifth conductive layer via a seven…d2
The semiconductor device according to claim 4, wherein the second conductive layer is electrically connected to the fifth conductive layer via a seventh contact hole disposed between overlapped portions of the second and fifth conductive layers in the plane view, and the first conductive layer is electrically connected to the sixth conductive layer via an eighth contact hole disposed between overlapped portions of the first and sixth conductive layers in the plane view.
›9.↳ 4The semiconductor device according to claim 4, wherein the one of the first pair of impurity regions and the second conductive layer are electrically …d2
The semiconductor device according to claim 4, wherein the one of the first pair of impurity regions and the second conductive layer are electrically connected to the fifth conductive layer via a first shared contact disposed between overlapped portions of the fifth conductive layer and the one of the first pair of impurity regions in the plane view, the one of the third pair of impurity regions is an impurity region common to the one of the fourth pair of impurity regions, and is electrically connected to the fifth conductive layer via a first contact hole disposed between overlapped portions of the fifth conductive layer and the one of the third pair of impurity regions in the plane view, the one of the eighth pair of impurity regions is electrically connected to the second conductive layer via a second shared contact, the one of the second pair of impurity regions and the first conductive layer are electrically connected to the sixth conductive layer via a third shared contact disposed between overlapped portions of the sixth conductive layer and the one of the second pair of impurity regions in the plane view, the one of the fourth pair of impurity regions is an impurity region common to the one of the seventh pair of impurity regions, and is electrically connected to the sixth conductive layer via a second contact hole disposed between overlapped portions of the sixth conductive layer and the one of the sixth impurity regions in the plane view, and the one of the sixth pair of impurity regions is electrically connected to the first conductive layer via a fourth shared contact.
›10.↳ 4The semiconductor memory according to claim 4, wherein the respective one electrodes in the first to fourth conductive layers are disposed separately.d2
The semiconductor memory according to claim 4, wherein the respective one electrodes in the first to fourth conductive layers are disposed separately.
›11.↳ 4The semiconductor memory according to claim 4, wherein the first and third conductive layers are arranged in an approximately straight line along the …d2
The semiconductor memory according to claim 4, wherein the first and third conductive layers are arranged in an approximately straight line along the direction of formation of the first word line, and the second and fourth conductive layers are arranged in an approximately straight line along the direction of formation of the second word line.
