Methods and apparatus for package on package devices

This application is a reissue application of U.S. Pat. No. 9,373,599.

This application is a continuation application of patent application Ser. No. 13/463,667, entitled “Methods and Apparatus for Package on Package Devices,” filed on May 3, 2012, which application is incorporated herein by reference.

Since the invention of the integrated circuit (IC), the semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (i.e., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area.

These smaller electronic components also require smaller packages that utilize less area than previous packages. Some smaller types of packages for semiconductors include quad flat pack (QFP), pin grid array (PGA), ball grid array (BGA), flip chips (FC), three dimensional integrated circuits (3DICs), wafer level packages (WLPs), and package on package (PoP) devices. Package on package (PoP) technology is becoming increasingly popular for its ability to allow for denser integration of integrated circuits into a small overall package. PoP technology is employed in many advanced handheld devices, such as smart phones.

In a PoP device, individual semiconductor dies may be packaged either separately or with multiple semiconductor dies in each separate individual package, and then the separate individual packages may be brought together and interconnected to form a PoP device so that the individual semiconductor dies in the separate individual packages may be integrated together in order to perform desired tasks. The separate individual packages may be electrically interconnected to each other, for example, by using contact bumps or other connectors. The heat dissipation and warpage control for PoP devices are issues to consider.

For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIGS. 1(a)-1(e) illustrate cross-sectional views of a package on package (PoP) device and a method for forming such a device in accordance with an embodiment; and

FIGS. 2(a)-2(e) illustrate cross-sectional views and top views of additional embodiments of PoP devices.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

The making and using of the embodiments of the present disclosure are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosure, and do not limit the scope of the disclosure.

As will be illustrated in the following, methods and apparatus for a package-on-package (PoP) device are disclosed. In short, an embodiment of a PoP device is formed by connecting a top package and a bottom package together using a plurality of PoP connectors on the bottom package connected to corresponding connectors of the top package. The PoP device further comprises a plurality of dummy connectors. A dummy connector is placed on the bottom package and is not connected to any corresponding connector in the top package. Therefore a dummy connector is not used for connection purposes. Instead, a dummy connector is used to reduce the molding compound volume in order to reduce the device warpage. Moreover, the dummy connector is made of metal, and can improve heat dissipation and stress redistribution. The dummy connector may be formed at the same time as the PoP connectors are formed.

FIG. 1(a) illustrates a cross-sectional view of two individual packages 10 and 20 , connected together to form a PoP device 100 as illustrated in FIG. 1(b) in accordance with an embodiment, using an exemplary method illustrated in FIG. 1(c) . More detailed intermediate steps are illustrated in FIGS. 1(d) and 1(e) .

As illustrated in FIG. 1(a) , a first package 10 , which may be a top package, has a first substrate 108 . A first integrated circuit (IC) die 106 is mounted on one surface of the substrate 108 , which may be the top surface of the substrate, via a set of conductive connectors 110 . Through vias (TVs) (not shown) may be used to provide electrical connections between the first die 106 and another set of conductive connectors 112 such as bond pads on an opposing surface of the substrate 108 , which may be the bottom surface of the substrate. An encapsulant or mold 114 may be formed over the components to protect the components from the environment and external contaminants. A plurality of connectors such as solder balls 221 to 224 may be formed on the bottom surface of the first substrate 108 . The connectors 221 to 224 may be used to connect to another package, such as a bottom package 20 . The connectors 221 to 224 are attached to the connectors 112 , which may be bond pads, on the bottom of the first substrate 108 . The number of connectors such as 112 , 110 , and the number of connectors such as 221 to 224 are only for illustrative purposes, and is not limiting. A connector may be a bond pad such as a connector 112 or a solder ball such as a connector 221 . As long as a component may provide an electronic connection, the component may be called a connector. There may be other number of connectors for the package 10 .

The first package 10 may package the die 106 using a flip-chip wafer level package (WLP) and wire bonding technique, or using a flip-chip and bump-on-trace (BOT) technique. Alternative package techniques may be used to form the package 10 . The substrate 108 may also include redistribution lines (RDLs) (not shown) within and/or on one or both surfaces of the substrate 108 to allow for a different pin configuration as well as larger electrical connections. The substrate 108 may be, for example, a packaging substrate, a printed-circuit board, a high-density interconnect, or the like. The die 106 may be a memory chip or a logic chip, for example. The set of connectors 110 and 112 may comprise, for example, contact pads, lead free solder, eutectic lead, conductive pillars, combinations thereof, and/or the like. If the connectors 221 to 224 are solder balls, they may be formed using a ball mount process, followed by a solder reflow process. The connectors 221 to 224 may alternatively be formed using other methods.

A second package 20 , which may be called a bottom package, comprises a second substrate 104 with a second IC die 102 mounted thereon on one surface of the substrate, which may be the top surface of the substrate 104 . The second die 102 may be of a logic function. The substrate 104 is connected to the die 102 by a set of connectors 116 and 120 . The connectors 116 may be bond pads and the connectors 120 may be a plurality of solder balls, which together form the connections between the die 102 and the substrate 104 . Another set of connectors 118 may be formed along an opposing surface of the second substrate 104 from the die 102 , which may be the bottom surface. TSVs 121 in the second substrate 104 may provide an electrical connection among the connectors 116 and the connectors 118 . A plurality of connectors such as solder balls 211 to 214 may be formed on the bottom surface of the substrate 104 . The substrate 104 may also include RDLs (not shown) within and/or on one or both surfaces of the second substrate 104 to allow for a different pin configuration as well as larger electrical connections.

In an embodiment, the substrate 104 may be any suitable substrate, such as a silicon substrate, an organic substrate, a ceramic substrate, a dielectric substrate, a laminate substrate, or the like. The connectors 116 , 120 , and 118 may comprise, for example, contact pads, lead free solder, eutectic lead, conductive pillars, combinations thereof, and/or the like. The die 102 may be any suitable integrated circuit die for a particular application. For example, the die 102 may be a memory chip, such as a DRAM, SRAM, NVRAM, or a logic circuit. There is only die 102 shown in FIGS. 1(a) and 1(b) . However, there may be a plurality of dies on the substrate 104 . Similarly, there may be a plurality of dies on the substrate 108 as well.

The first package 10 and the second package 20 may be electrically coupled to form a package-on-package (PoP) device 100 as shown in FIG. 1(b) . A set of connectors such as 31 to 36 may be formed on the top surface of the substrate 104 , which is the same surface where the die 102 is mounted. The connectors 31 to 34 , which may be called as PoP connectors, are formed according to the pattern of the connectors 221 to 224 of the top package 10 , meaning PoP connectors 31 to 34 are aligned with connectors 221 to 224 , respectively. The connectors 35 and 36 are extra connectors, sometimes referred to herein as dummy connectors, that do not correspond to and are not connected to any connectors of the top package 10 . The connectors 31 to 34 may be further connected to some bond pads on the substrate 104 , which are connected to other internal functions of the chip 102 or the substrate 104 . The connectors 35 and 36 on the other hand, may not be connected to any other functions or bond pads. All the connectors 31 to 36 are further covered by an encapsulant or mold 230 to protect the components from the environment and external contaminants. The encapsulant 230 is then grinded to expose the connectors 31 to 34 . Afterwards, the top package 10 may be aligned and attached so that the connectors 31 to 34 are connected to the connectors 221 to 224 in an one to one correspondence fashion.

The connectors 35 and 36 illustrated in FIG. 1(b) are called dummy connectors, or dummy balls. In short, a dummy connector at a bottom package is a connector that is not connected to any corresponding connector in the top package, therefore a dummy connector or a dummy ball is not used for connection purposes as the PoP connectors are. Instead, dummy connectors are used to reduce the molding compound volume in order to reduce the package warpage. Moreover, the dummy connectors are made of metals, and they can improve heat dissipation and stress redistribution.

FIG. 1(c) illustrates a flow chart of an exemplary process of packaging semiconductor devices in accordance with an embodiment of the present disclosure. In step 301 , a plurality of connectors such as solder balls is mounted on a surface of a substrate of the bottom package, which may be the top surface of the substrate. Some connectors form a pattern designed as the connector pattern for the top package, which are called PoP connectors. Some other connectors are dummy connectors not corresponding to the pattern of the connectors for the top package. In step 303 , the substrate surface with the connectors, both the PoP connectors and the dummy connectors, are molded with an encapsulant such as molding materials. In step 305 , the encapsulant is grinded to expose the PoP connectors so that they can be connected to the connectors of the top package. Dummy connectors may be exposed by this process as well. In step 307 , the top package is aligned so that the connectors of the top package are placed on top of the PoP connectors of the bottom package and connections to the PoP connectors can be made. Afterwards, in step 309 , the formed package is reflowed to form connections between the PoP connectors and the connectors of the top package.

FIG. 1(d) illustrates an example step 301 showing a set of connectors such as 31 to 36 may be formed on the top surface of the substrate 104 of the bottom package 20 . The connectors 31 to 34 are PoP connectors, which are formed according to the pattern of the connectors 221 to 224 of the top package 10 . The connectors 35 and 36 are the dummy connectors which do not correspond to any connectors of the top package 10 . The connectors 31 to 34 may be further connected to some connectors on the substrate 104 , which are connected to other internal functions of the chip 102 or the substrate 104 . The connectors 35 and 36 on the other hand, may not be connected to any other functions. The connectors or the balls 31 to 36 may comprise a material such as tin, or other suitable materials, such as silver, lead-free tin, copper, combinations thereof, or the like.

FIG. 1(e) illustrates an example step 303 showing the formation of a molding encapsulant 230 applied on the second substrate 104 in accordance with an embodiment. In an embodiment, the molding encapsulant 230 is a molding underfill (MUF) comprising, for example, a polymer, epoxy, and/or the like. The molding encapsulant 230 may be molded onto the die 102 and the substrate 104 using, for example, compressive molding or transfer molding. The molding encapsulant 230 may be in contact with the top surface and the edges of the die 102 . In one embodiment, a top surface of the molding encapsulant 230 may be coplanar with a top surface of the die 102 . In other embodiments, a top surface of the molding encapsulant 230 may be higher than a top surface of the die 102 such that the die 102 may be fully encapsulated in the molding encapsulant 230 .

At step 305 , a grinding or polishing process may be performed to remove portions of the molding encapsulant 230 from over a top surface of the die 102 to expose the die 102 . The molding encapsulant 230 is also grinded to expose the PoP connectors 31 to 34 so that they can be connected to the connectors of the top package. In addition, not shown, a flux may be applied to the surface of the molding encapsulant 230 and the connectors 31 to 34 . The flux helps clean the surface of the molding encapsulant 230 and the PoP connectors 31 to 34 , thereby aiding in formation of an electrical contact between the PoP connectors 31 to 34 and the connectors 221 and 224 . The flux may be applied by, for example, in a dipping operation in which the surface of the molding compound 230 and the connectors 31 to 34 is dipped in a flux.

In step 307 , the top package is aligned so that the connectors 221 to 224 of the top package are placed on top of the PoP connectors 31 to 34 of the bottom package. The method includes coupling each of the plurality of connectors 221 to 224 of the top package to one of the plurality of connectors 31 to 34 on the top surface of the second substrate of the bottom package.

Afterwards, in step 309 , the formed package is reflowed to form connections between the PoP connectors 31 to 34 of the bottom package and the connectors 221 to 224 of the top package. In an embodiment, the reflow process is performed using an induction reflow process. In other embodiments, however, other reflow processes may also be used. The result is a PoP device as shown in FIG. 1(b) .

Following a similar process, further embodiments may be constructed. FIGS. 2(a)-2(e) illustrate cross-sectional views and top views of additional embodiments of PoP devices. FIG. 2(a) is a top view of the top package, while FIG. 2(b) shows the cross-section view of the top package. The top package may be packaged using a flip-chip WLP and wire bonding technique, or using a flip-chip and BOT technique. Alternative package techniques may be used to form the top package.

FIGS. 2(c) and 2(e) illustrate top views of the bottom package of a PoP device, while FIG. 2(d) illustrates a cross-section view of the bottom package. The bottom package has two rows of PoP connectors 400 , which may be ball arrays, surrounding the peripheral region of the substrate of the bottom package, forming two rings, corresponding to the connectors 400 of the top package shown in FIG. 2(a) . A plurality of dummy connectors 401 to 404 , 501 to 504 , and 601 to 602 may be placed on the top surface of the bottom package. The number of dummy connectors is only for illustration purposes and is not limiting. Alternatively, other numbers of balls may be used.

The dummy connectors 401 to 404 aligned on line A are placed close to the PoP connectors. FIG. 2(d) shows the cross section view of the four dummy balls 401 to 404 formed, together with two PoP connectors on each side. The connectors 501 to 504 aligned on line B are placed close to the chip 102 . FIG. 2(d) shows the cross section view of the four dummy connectors 501 to 504 formed, together with two PoP connectors on each side. The connectors 601 to 602 aligned on line C are placed close to chip 102 , and a cross section view of the connectors 601 and 602 also include the chip 102 . The connectors 601 and 602 are also surrounded by the two PoP connectors on each side.

FIG. 2(e) further illustrates a top view of the bottom package for an embodiment of a PoP device, wherein a plurality of dummy connectors is formed. Some of the dummy connectors are placed around the rings of the PoP connectors, while some others are placed in the middle positions. Some of the dummy connectors such as connectors 701 may be smaller than some other dummy connectors 702 .

It should be understood that the above description provides a general description of embodiments and that embodiments may include numerous other features. For example, embodiments may include under bump metallization layers, passivation layers, molding compounds, additional dies and/or substrates, and the like. Additionally, the structure, placement, and positioning of the die 106 and the die 102 are provided for illustrative purposes only, and accordingly, other embodiments may utilize different structures, placements, and positions.

It should also be understood that the ordering of the various steps discussed above are provided for illustrative purposes only, and as such, other embodiments may utilize different sequences. These various orderings of the step are to be included within the scope of embodiments.

Thereafter, other normal processes may be used to complete the device 100 . For example, the second substrate 104 may be attached to yet another substrate, such as a printed circuit board (PCB), a high-density interconnect, a silicon substrate, an organic substrate, a ceramic substrate, a dielectric substrate, a laminate substrate, another semiconductor package, or the like.

Although embodiments of the present disclosure and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present disclosure. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.