Elastic membrane for semiconductor wafer polishing

FIG. 1 is a front view of an elastic membrane for semiconductor wafer polishing showing our new design;

FIG. 2 is a rear view thereof;

FIG. 3 is a bottom view thereof;

FIG. 4 is a plan view thereof;

FIG. 5 is a left side view thereof;

FIG. 6 is a right side view thereof;

FIG. 7 is a cross-section view taken along the line 7 - 7 of FIG. 2 thereof;

FIG. 8 is a enlarged view of part 8 of FIG. 7 thereof; and,

FIG. 9 is a enlarged perspective view, observed from above thereof.

The broken lines depict environmental subject matter only and form no part of the claimed design.