Transistor substrate
Granted 5 Jun 2001 · no office action yet
Assignee: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho
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Attorney: Attorney · Log in to unlock
Inventors: Toshiaki Nagase, Jun Ishikawa · Examiner: Brian N. Vinson · AU 2911 · TC 2900
Life of the patent
4 dated eventsDescription
1 parts›FIG. 1 is a front elevational view showing…
FIG. 1 is a front elevational view showing a transistor substrate according to a first embodiment of the present invention;
FIG. 2 is a rear elevational view of the substrate of FIG. 1;
FIG. 3 is a top plan view of the substrate of FIG. 1;
FIG. 4 is a bottom plan view of the substrate of FIG. 1;
FIG. 5 is a right side elevational view of the substrate of FIG. 1, the left side elevational view being a mirror image of the right side elevational view;
FIG. 6 is a top front perspective view of the substrate of FIG. 1;
FIG. 7 is a top plan view showing a transistor substrate according to a second embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment;
FIG. 8 is a top front perspective view of the substrate of FIG. 7;
FIG. 9 is a top plan view showing a transistor substrate according to a third embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment;
FIG. 10 is a top front perspective view of the substrate of FIG. 9;
FIG. 11 is a top plan view showing a transistor substrate according to a fourth embodiment of the present invention, wherein the front elevational view, the rear elevational view, the bottom plan view, the right side elevational view and the left side elevational view are identical with those of the first embodiment; and,
FIG. 12 is a top front perspective view of the substrate of FIG. 11.
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