A semiconductor device and a method of fabricating the semiconductor device are provided. The semiconductor device includes a substrate, a gate structure over the substrate, a source/drain regions adjacent to the pair of spacers in the substrate, an etch stop layer next to the gate structure and overlying the substrate, a contact plug extending into the source/drain region and partially overlapping the gate structure, a protective layer over the etch stop layer overlying the substrate and covering the etch stop layer next to the gate structure without the contact plug, and an interlayer dielectric layer over the protective layer. The contact plug has no contact-to-gate short issue to the gate structure.

Claims

20 · 3 independent · depth 3

20 granted claims

›1.independentA method of fabricating semiconductor device comprising:nforming a gate structure with a dummy gate electrode and a source/drain regions adjacent to t…+4

›6.independentA method of fabricating semiconductor device comprising:nforming a dummy gate structure with a dummy gate electrode and source/drain regions adjacent …+8

›7.↳ 6The method of claim 6, further comprising annealing the interlayer dielectric layer, after polishing the etch stop layer to expose the dummy gate stru…d2

›8.↳ 6The method of claim 6, wherein in depositing an etch stop layer over the dummy gate structure, the etch stop layer overlies the dummy gate structure a…d2+3

›9.↳ 6The method of claim 6, wherein in depositing the protective layer over the etch stop layer, the protective layer conformally overlies the etch stop la…d2

›13.↳ 6The method of claim 6, wherein in forming the contact opening through the interlayer dielectric layer, the contact opening exposes the isolation layer…d2

›14.↳ 6The method of claim 6, wherein in forming the dummy gate structure with the dummy gate electrode and the source/drain regions, the dummy gate structur…d2

›15.independentA method of fabricating semiconductor device comprising:nforming a dummy gate structure with a dummy gate electrode and source/drain regions adjacent …+5

Classifications

6 codes

IPC · International Patent Classification

Section H — Electricity

H01L21/336
H01L21/3105
H01L29/417
H01L21/768
H01L21/28
H01L29/66

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Pendency

0.6 y

204 days filing → grant

Office actions

none on record

Examiner

David S Blum

art unit 2813 · TC 2800

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Citations: 10 back · 0 forward

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Priority chain

1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20160087076 A1	24 Mar 2016

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