Compliant dielectric layer for semiconductor device

An integrated circuit (IC) package, comprising:na semiconductor material body having opposing first and second surfaces, and including a first electrically conductive feature at the first surface;a compliant dielectric material layer having opposing first and second surfaces, the first surface of the compliant dielectric material layer on the second surface of the semiconductor material body, the compliant dielectric material layer having a deformability that is greater than a deformability of the semiconductor material body;a second electrically conductive feature formed on the second surface of the compliant dielectric material layer;an electrically conductive via formed through the semiconductor material body and the compliant dielectric material layer that electrically couples the first electrically conductive feature to the second electrically conductive feature;a passivation layer between the compliant dielectric material layer and the semiconductor material body, and between the compliant dielectric material layer and the electrically conductive via, the electrically conductive via within the semiconductor material body lacking the passivation layer; andan interconnect member coupled to the second surface of the compliant dielectric material layer in electrical contact with the second electrically conductive feature.

The IC package of claim wherein the semiconductor material body includes an active integrated circuit.

The IC package of claim I, wherein the compliant dielectric material layer comprises:na plurality of compliant dielectric material sub-layers.

An integrated circuit (IC) package, comprising:nan interposer having opposing first and second surfaces, that comprises:na semiconductor material body having opposing first and second surfaces;a compliant dielectric material layer having opposing first and second surfaces, the first surface of the compliant dielectric material layer on the second surface of the semiconductor material body, the compliant dielectric material layer having a deformability that is greater than a deformability of the semiconductor material body, the compliant dielectric material layer comprising a plurality of compliant dielectric material sub-layers;a first electrically conductive via and a second electrically conductive via each formed through the semiconductor material body and the compliant dielectric material layer; andat least one IC die mounted to the first surface of the interposer.

A semiconductor device, comprising:na semiconductor material body having opposing first and second surfaces;a compliant dielectric material layer having opposing first and second surfaces, the first surface of the compliant dielectric material layer on the second surface of the semiconductor material body, the compliant dielectric material layer having a deformability that is greater than a deformability of the semiconductor material body the compliant dielectric material layer comprising a plurality of compliant dielectric material sub-layers;an electrically conductive via passing through the semiconductor material body and the compliant dielectric material layer and in electrical contact with a metal layer on the first surface of the semiconductor material body, a first sub-layer of the plurality of compliant dielectric material sub-layers being between the electrically conductive via and a second sub-layer of the plurality of compliant dielectric material sub-layers; andan interconnect member coupled to the second surface of the compliant dielectric material layer in electrical contact with the electrically conductive via.