Level switching circuit and method for controlling rail-to-rail enabling signal

The circuit for controlling the Rail-to-Rail enabling signal of claim 9, wherein the level switching circuit includes:nan NMOS (M12) including a gate, a drain, a source, and a substrate,wherein the NMOS (M12) is configured to pull down the level of the enabling signal output node when the power supply has a normal voltage and the input signal is in the low level, andwherein the substrate of the NMOS (M12) is connected to the disabling signal providing node,wherein the gate and the drain of the NMOS (M12) are both connected to the source of the NMOS (M11) and to the resistor (R3), andwherein the source of the NMOS (M12) is connected to a power supply ground.

The circuit for controlling the Rail-to-Rail enabling signal of claim 9, wherein the buffer is configured to acquire the second signal and to provide a representation of the second signal to the gate of the NMOS (M11).

The method for controlling the Rail-to-Rail enabling signal of claim 18, wherein the performing, by the level switching circuit, enabling control according to high and low levels of the first and the second buffered input signals includes:nturning both the PMOS (M10) and the NMOS (M11) on and outputting, by an enabling signal output node, an enabling signal when the power supply has a normal voltage VCC, the input signal is high, the first buffered input signal provided to the drain of the PMOS (M10) is high, and the second buffered input signal provided to the gate of the NMOS (M11) is low; andturning the PMOS (M10) off and the NMOS (M11) on, pulling down the level of the enabling signal output node to the level Vnrail of a disabling signal providing node providing the disable signal via a resistor (R3) in the level switching circuit, and outputting, by the enabling signal output node, the disabling signal when the power supply has the normal voltage VCC, the input signal is low, the first buffered input signal provided to the drain of the PMOS (M10) is high, and second buffered input signal provided to the gate of the NMOS (M11) is low.

The method for controlling the Rail-to-Rail enabling signal of claim 18, wherein the outputting, by the level switching circuit, a disabling signal in case of the failure of the power supply failure includes:nturning the PMOS (M10) off and the NMOS (M11) on, pulling down the level of the enabling signal output node to the level Vnrail of a disabling signal providing node providing the disable signal via a resistor (R3), and outputting, by the enabling signal output node, the disabling signal when the power supply fails, the buffer stops operating, and both the first buffered input signal provided to the drain of the PMOS (M10) and the second buffered input signal provided to the gate of the NMOS (M11) are low.