Level switching circuit and method for controlling rail-to-rail enabling signal

This application claims the benefit of priority under 35 U.S.C. 119 to Chinese Patent Application Serial No. 201210062731.X, filed on Mar. 7, 2012, which is incorporated by reference herein in its entirety.

The disclosure relates to techniques for controlling an enabling signal, in particular to a method and a circuit for controlling a Rail-to-Rail enabling signal, and a level switching circuit therein.

As different operating voltages emerge for digital Integrated Circuits (IC), the need for logic level switching increasingly stands out. Level switching can vary with logic level, data bus form, or data transmitting rate. In certain examples, data bus form can include four-wire Serial Peripheral Interface (SPI), 32-bit parallel data bus, and the like. At present, there are a number of logic chips that can be used to control a Rail-to-Rail enabling signal. However, many of such logic chips stop operating when losing power, which may cause errors in the Rail-to-Rail enabling signal.

FIG. 1 illustrates an example of a circuit that can be used to control a Rail-to-Rail enabling signal, including Positive Channel Metal-Oxide-Semiconductor Field-Effect Transistors (PMOS) M 1 , M 3 , M 5 , M 7 , and M 8 , Negative Channel Metal-Oxide-Semiconductor Field-Effect Transistors (NMOS) M 2 , M 4 , M 6 , and M 9 , and resistors R 1 and R 2 .

The PMOS M 1 has a substrate and a source both connected to a power supply pwrin, a gate receiving an input signal in, and a drain connected to a drain of the NMOS M 2 and to a gate of the PMOS M 5 . The NMOS M 2 has a substrate and a source both connected to the power supply ground pwrn, a gate receiving an input signal in, and a drain connected to the drain of the PMOS M 1 and to the gate of the PMOS M 5 .

The PMOS M 3 has a substrate and a source both connected to the power supply pwrin, a gate receiving input signal in, and a drain connected to the resistor R 1 and to a gate of the NMOS M 6 . The resistor R 1 is connected, at one end, to the drain of the PMOS M 3 and to a gate of the NMOS M 6 , and, at the other end, to a drain of the NMOS M 4 . The NMOS M 4 has a drain connected to the resistor R 1 , a gate connected to a drain of the PMOS M 5 , a source connected to the power supply ground pwrn and a disabling signal providing node nrail, and a substrate connected to the power supply ground pwrn. The PMOS M 5 has a substrate and a source both connected to the power supply pwrn, a gate connected to the drain of the PMOS M 1 and to the drain of the NMOS M 2 , and a drain connected to the resistor R 2 , to the gate of the NMOS M 4 , to the drain of the PMOS M 7 , and to the gate of the PMOS M 8 . The resistor R 2 is connected, at one end, to the drain of the PMOS M 5 and to the gate of the NMOS M 4 , and, at the other end, connected to the drain of the NMOS M 6 . The NMOS M 6 has a drain connected to the resistor R 2 , a gate connected to the drain of the PMOS M 3 , a source connected to the power supply pwrn and to the disabling signal providing node nrail, and a substrate connected to the power supply pwrn.

The PMOS M 7 has a substrate and a source both connected to the power supply pwrn, a gate connected to an enabling signal providing node eni_rr, and a drain connected to the resistor R 2 , to the gate of the NMOS M 4 , to the drain of the PMOS M 5 , and to the gate of the PMOS M 8 . The PMOS M 8 has a substrate and a source both connected to the power supply pwrin, a gate connected to the resistor R 2 , to the gate of the NMOS M 4 , to the gate of the NMOS M 9 , to the drain of the PMOS M 5 , and to the drain of the PMOS M 7 , and a drain connected to the enabling signal providing node eni_rr. The NMOS M 9 has a gate connected to the source, to the power supply pwrn and to the disabling signal providing node nrail, a substrate connected to the power supply pwrn, a gate connected to the resister R 2 , to the gate of the NMOS M 4 , to the gate of the PMOS M 8 , to the drain of the PMOS M 5 and to the drain of the PMOS M 7 , and a drain connected to the enabling signal providing node eni_rr. The gate of the PMOS M 8 and the gate of the NMOS M 9 are also connected to a signal gate.

In FIG. 1 , when the voltage VCC of the power supply pwrin is normal, the enabling signal providing node eni_rr can output a corresponding Rail-to-Rail enabling control signal, such as the voltage VCC of the output power supply pwrin or the voltage Vnrail of the disabling signal providing node nrail, according to the high and low levels of the input signal in. When the power is down, the PMOS M 3 and the PMOS M 5 may not be in a stable state, which can cause the entire circuit to be unable to operate properly. As a result, the enabling signal output node eni_rr may be unable to reach the voltage Vnrail of the disabling signal providing node nrail, and thus may be unable to provide an accurate enabling control signal to equipment operated under the control of the enabling control.

The present inventors have recognized, among other things, a method and a circuit for controlling a Rail-to-Rail enabling signal and a level switching circuit therein. A first signal of an input signal of a control circuit can be fed in a level switching circuit, wherein the level switching circuit perform enabling control according to high or low levels of the first signal, and the level switching circuit outputs a disabling signal in case of a failure of a power supply. Thus, the level switching circuit can output a Rail-to-Rail enabling or disabling signal according to high and low levels of the first signal when the power supply voltage is normal and can output a disabling signal according to a low level output into which the first signal changes in case of the failure of the power supply, thereby providing an accurate enabling control signal for an equipment operated under the control of the enabling control.

A level switching circuit can include a PMOS having a drain configured to receive a first signal of an input signal. The PMOS can be in a state of on or off according to a high level or a low level of the first signal, wherein, in case of power supply failure, the input signal is in the low level. The level switching circuit can include a resistor configured to enable a signal output node to output an enabling signal when the PMOS is on and to enable the signal output node to output a disabling signal when the PMOS is off.

A circuit for controlling a Rail-to-Rail enabling signal can include a level switching circuit configured to receive a first signal of an input signal, to perform enabling control according to a high level and a low level of the first signal, and to output a disabling signal in case of a failure of a power supply.

A method for controlling a Rail-to-Rail enabling signal can include feeding a first signal of an input signal of a control circuit to a level switching circuit, performing, by the level switching circuit, enabling control according to a high level and a low level of the first signal, and outputting, by the level switching circuit, a disabling signal in case of a failure of a power supply.

FIG. 1 is a schematic view of a circuit for controlling a Rail-to-Rail enabling signal in prior art;

FIG. 2 is a flowchart of an example method for controlling a Rail-to-Rail enabling signal according to the present disclosure;

FIG. 3 is a schematic view of a circuit for controlling a Rail-to-Rail enabling signal according to the present disclosure;

FIG. 4 is a schematic view of another circuit for controlling a Rail-to-Rail enabling signal according to the present disclosure;

FIG. 5 is a schematic view of a simulation test of a circuit for controlling a pair of Rail-to-Rail enabling signals according to the present disclosure; and

FIG. 6 is a schematic view of a simulation test of a circuit for controlling another pair of Rail-to-Rail enabling signals according to the present disclosure.

In an example, a first signal of an input signal of a control circuit can be fed to a level switching circuit, which can perform an enabling control according to high and low levels of the first signal and can output a disabling signal in case of a power supply failure. Specifically, when the power supply has a normal voltage, the level switching circuit can output an enabling signal according to the high level of the first signal and can output a disabling signal according to the low level of the first signal. In case of a power supply failure, the level switching circuit can output a disabling signal directly according to the low level of the first signal.

FIG. 2 illustrates generally a flowchart of an example method for controlling a Rail-to-Rail enabling signal. At 101 , the first signal of an input signal of a control circuit can be fed to a level switching circuit.

As illustrated in FIG. 3 , the first signal eni of the input signal of the control circuit can be acquired via a buffer 31 , and the first signal eni is fed to the drain of a PMOS M 10 of a level switching circuit 32 . The level switching circuit 32 can include phase inverters op 1 and op 2 . The input of the phase inverter op 1 can receive the input signal in, and the output of the phase inverter op 1 can be connected to the input of the phase inverter op 2 . The output of the phase inverter op 2 can be connected to the drain of the PMOS M 10 of the level switching circuit 32 . The grounding legs and the power supply legs of the phase inverters op 1 and op 2 can be connected to a power supply pwrin and a power supply ground pwrn, respectively.

The level switching circuit 32 can include the PMOS M 10 and a resistor R 3 , wherein the substrate of the PMOS M 10 can be connected to the power supply pwrin, the drain of the PMOS M 10 can be connected to the first signal eni of the input signal in, the source of the PMOS M 10 can be connected to an enabling signal providing node eni_rr and the resistor R 3 , and the gate of the PMOS M 10 can be connected to the power supply ground pwrn. R 3 can be connected between the source of the PMOS M 10 and a disabling signal providing node nrail.

In an example, at 101 , a second signal of the input signal can be fed to the level switching circuit. As illustrated in FIG. 4 , the second signal eni_bar of the input signal in can be acquired via buffer 31 and fed to the gate of an NMOS M 11 of the level switching circuit 32 . The level switching circuit 32 can include the NMOS M 11 for limiting the current through resistor R 3 . The NMOS M 11 can be arranged between the PMOS M 10 and the resistor R 3 , wherein the substrate of the NMOS M 11 can be connected to the disabling signal providing node nrail, the drain of the NMOS M 11 can be connected to the source of the PMOS M 10 , the source of the NMOS M 11 can be connected to the resistor R 3 , and the gate of the NMOS M 11 can be connected to the second signal eni_bar of the input signal in.

The level switching circuit 32 can include an NMOS M 12 , wherein the substrate of the NMOS M 12 can be connected to the disabling signal providing node nrail, the drain and the gate of the NMOS M 12 can be connected to the source of the NMOS M 11 and to the resistor R 3 , and the gate of the NMOS M 12 can be connected to the power supply ground pwrn. The NMOS M 12 can be configured to promptly pull down the level of the enabling signal output node eni_rr.

At 102 , the level switching circuit can perform enabling control according to high and low levels of the first signal and can output a disabling signal in case of a power supply failure.

As illustrated in FIG. 3 , assuming there is no NMOS M 11 , such as that illustrated in FIG. 4 , for limiting the current through the resistor R 3 in the level switching circuit 32 , when the voltage VCC of power pwrin is normal and the input signal in is high, the first signal eni fed to level switching circuit 32 can be high VCC, the PMOS M 10 can be on, and the enabling signal output node eni_rr can output the enabling signal VCC. When voltage VCC of power pwrin is normal and the input signal in is low, the first signal eni fed to level switching circuit 32 can be low (0), the PMOS M 10 can be off, the level of the enabling signal output node eni_rr can be pulled down to the level Vnrail of the disabling signal providing node nrail via the pull-down resister R 3 , and the enabling signal output node eni_rr can output the disabling signal Vnrail.

In case of a power supply failure, the buffer 31 can stop operating, the first signal eni fed to the level switching circuit 32 can be low (0) irrespective of the voltage of the input signal in, the PMOS M 10 can be cut off, the level of the enabling signal output node eni_rr can be pulled down to the level Vnrail of the disabling signal providing node nrail via the resistor R 3 , and the enabling signal output node eni_rr can output the disabling signal Vnrail.

When the level switching circuit 32 includes the NMOS M 11 for limiting the current through the resistor R 3 , such as illustrated in FIG. 4 , the level switching circuit 32 can perform enabling control according to high and low levels of the first and second signals.

As shown in FIG. 4 , when the power supply pwrin has a normal voltage VCC and the input signal in is high, the first signal eni fed to the level switching circuit 32 is high VCC, the second signal eni_bar is low 0, the PMOS M 10 is on, based on the fact that the level Vnrail of the node nrail providing the disabling signal is smaller than a negative turning-on threshold of the NMOS M 11 , the NMOS M 11 can be on and the enabling signal output node eni_rr can output the enabling signal VCC. When the power supply pwrin has the normal voltage VCC and the input signal in is low, the first signal eni fed in the level switching circuit 32 is low 0, the second signal eni_bar is high VCC, the PMOS M 10 is cut off, the NMOS M 11 is on, the level of the enabling signal output node eni_rr is pulled down to the level Vnrail of disabling signal providing node nrail via the pull-down resistor R 3 , and the enabling signal output node eni_rr can output the disabling signal Vnrail.

In case of a power supply failure, the buffer 31 can stop operating and the first and the second signals eni, eni_bar fed in the level switching circuit 32 are low (0). The PMOS M 10 can be cut off, based on the fact that the level Vnrail of the node nrail providing the disabling signal is smaller than the negative turning-on threshold of the NMOS M 11 , and the NMOS M 11 can be on. The level of the enabling signal output node eni_rr can be pulled down to the level Vnrail of disabling signal providing node nrail via the resistor R 3 and the enabling signal output node eni_rr can output the disabling signal Vnrail.

In an example, at 202 , the level of the enabling signal output node eni_rr can promptly pull down via the NMOS M 12 when the power supply pwrin has the normal voltage VCC and the input signal in is low. In the aforementioned method, the first signal is the positive signal of the input signal and the second signal is the inverted signal of the input signal.

To implement the method for controlling a Rail-to-Rail enabling signal as described herein, the level switching circuit 32 , as shown in FIG. 3 , can include the PMOS M 10 and the resistor R 3 , wherein the PMOS M 10 is configured to receive a first signal eni of an input signal in at its drain, wherein the PMOS M 10 is in a state of on or off according to respective high and low levels of the first signal eni, wherein the first signal eni is low in case of a power supply pwrin failure. The level switching circuit 32 can further include the resistor R 3 configured to enable an enabling signal output node eni_rr to output an enabling signal when the PMOS M 10 is on and to enable the enabling signal output node eni_rr to output a disabling signal when the PMOS M 10 is off.

In an example, the specific connection relation of the PMOS M 10 and resistor R 3 is as follows. The substrate of the PMOS M 10 is connected to the power supply pwrin, the drain of the PMOS M 10 is connected to the first signal eni of the input signal in, a source of the PMOS M 10 is connected to the resistor R 3 , and a gate of the PMOS M 10 is connected to a power supply ground pwrn. The resistor R 3 is between the source of the PMOS M 10 and a disabling signal providing node nrail and the level of the disabling signal providing node nrail is no higher than the power supply ground pwrn.

As shown in FIG. 4 , the level switching circuit 32 can further include NMOS M 11 configured to receive a second signal eni_bar of the input signal in at its source and can control the NMOS M 11 to be in a state of break-over and limit the current through the resistor R 3 when the power supply pwrin either has a normal voltage or is down. The NMOS M 11 can be arranged in between the PMOS M 10 and the resistor R 3 , and the substrate of the NMOS M 11 can be connected to a disabling signal providing node nrail, the drain of the NMOS M 11 can be connected to the source of the PMOS M 10 , the source of the NMOS M 11 can be connected to the resistor R 3 , and the gate of the NMOS M 11 can be connected to the second signal eni_bar of the input signal in.

The level switching circuit 32 can further include an NMOS M 12 configured to promptly pull down the level of the enabling signal output node eni_rr when the power supply pwrin has a normal voltage VCC and the input signal in is in the low level. In an example, the substrate of the NMOS M 12 is connected to the disabling signal providing node nrail, both the gate and the drain of the NMOS M 12 are connected to the source of the NMOS M 11 and to the resistor R 3 , and the source of the NMOS M 12 is connected to a power supply ground pwrn.

FIG. 3 illustrates generally a circuit for controlling a Rail-to-Rail enabling signal including a level switching circuit 32 configured to receive a first signal eni of an input signal in, to perform enabling control according to high and low levels of the first signal eni, and to output a disabling signal in case of a power supply pwrin failure. The level switching circuit 32 can include a PMOS M 10 and a resistor R 3 , wherein the PMOS M 10 is configured to receive first signal eni of input signal in at a drain and can control the PMOS M 10 to be in a state of on or off according to high and low levels of the first signal eni, wherein the first signal eni is in the low level in case of a power supply pwrin failure. The resistor R 3 is configured to enable an enabling signal output node eni_rr to output an enabling signal while the PMOS M 10 is on and to enable the enabling signal output node eni_rr to output a disabling signal during the PMOS M 10 is off.

An example specific connection relation of the PMOS M 10 and resistor R 3 follows. The substrate of the PMOS M 10 is connected to the power supply pwrin, the drain of the PMOS M 10 is connected to the first signal eni of the input signal in, a source of the PMOS M 10 is connected to the resistor R 3 , and a gate of the PMOS M 10 is connected to a power supply ground pwrn. The resistor R 3 is between the source of the PMOS M 10 and a disabling signal providing node nrail and the level of the disabling signal providing node nrail is no higher than the power supply ground pwrn;

FIG. 4 illustrates generally an example level switching circuit 32 , such as illustrated in FIG. 3 , further including an NMOS M 11 configured to receive a second signal eni_bar of the input signal in at its source and configured to control the NMOS M 11 in an on state and to limit the current through the resistor R 3 when the power supply pwrin either has a normal voltage or is down. In an example, the NMOS M 11 is arranged between the PMOS M 10 and the resistor R 3 , and the substrate of the NMOS M 11 is connected to a disabling signal providing node nrail, the drain of the NMOS M 11 is connected to the source of the PMOS M 10 , the source of the NMOS M 11 is connected to the resistor R 3 , and the gate of the NMOS M 11 is connected to the second signal eni_bar of the input signal in.

The level switching circuit 32 can include an NMOS M 12 configured to promptly pull down the level of the enabling signal output node eni_rr when the power supply pwrin has a normal voltage VCC and the input signal in is in the low level. The substrate of the NMOS M 12 can be connected to the disabling signal providing node nrail, both the gate and the drain of the NMOS M 12 can be connected to the source of the NMOS M 11 and to the resistor R 3 , and the source of the NMOS M 12 can be connected to a power supply ground pwrn.

As illustrated in FIG. 3 , the circuit for controlling a Rail-to-Rail enabling signal can include a buffer 31 configured to acquire the first signal eni of the input signal in and to feed the first signal eni to the drain of the PMOS M 10 of the level switching circuit 32 . As illustrated in FIG. 4 , the buffer 31 can further be configured to acquire the second signal eni_bar of the input signal in and feed the second signal eni_bar to the gate of the NMOS M 11 of the level switching circuit 32 .

FIGS. 5 and 6 illustrate generally simulation tests for an example circuit for controlling a Rail-to-Rail enabling signal described herein, such as illustrated in FIG. 4 , wherein the example circuit can output a disabling signal at all times, providing an accurate enabling control signal for an equipment operated under the control of the enabling control.

FIG. 5 illustrates generally a power supply voltage VCC=0V, an input signal Vin=−2V, a disabling signal providing node nrail of Vnrail=−2V, detection being done 6 times within 1 s, and an output disabling signal Vout=Vnrail=−2V.

FIG. 6 illustrates generally a power supply voltage VCC=0V, an input signal Vin=2V, a disabling signal providing node nrail of Vnrail=0V, detection being done 6 times within 1 s, and all output disabling signals are Vout=Vnrail=1.51408 nV≈0V.

What being described above are merely preferred embodiments of the disclosure and are not intended to limit the scope of the disclosure.

The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” Such examples can include elements in addition to those shown or described. However, the present inventor also contemplates examples in which only those elements shown or described are provided. Moreover, the present inventor also contemplates examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

All publications, patents, and patent documents referred to in this document are incorporated by reference herein in their entirety, as though individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated reference(s) should be considered supplementary to that of this document, for irreconcilable inconsistencies, the usage in this document controls.

In this document, the terms “a” or “an” are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of “at least one” or “one or more.” In this document, the term “or” is used to refer to a nonexclusive or, such that “A or B” includes “A but not B,” “B but not A,” and “A and B,” unless otherwise indicated. In this document, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein.” Also, in the following claims, the terms “including” and “comprising” are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms “first,” “second,” and “third,” etc. are used merely as labels, and are not intended to impose numerical requirements on their objects.

Method examples described herein can be machine or computer-implemented at least in part. Some examples can include a computer-readable medium or machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. An implementation of such methods can include code, such as microcode, assembly language code, a higher-level language code, or the like. Such code can include computer readable instructions for performing various methods. The code may form portions of computer program products. Further, in an example, the code can be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, such as during execution or at other times. Examples of these tangible computer-readable media can include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or sticks, random access memories (RAMs), read only memories (ROMs), and the like.

The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. §1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.