Integrated circuit arrangements with ESD-resistant capacitor and corresponding method of production
Granted 26 Jul 2011 · 2 office actions
Assignee: Infineon Technologies AG
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Inventors: Christian Russ, Harald Gossner, Jens Schneider, Kai Esmark · Examiner: Tanika Warrior
Life of the patent
9 dated eventsAbstract
A circuit arrangement including a capacitor in an n-type well is disclosed. A specific polarization of the capacitor ensures that a depletion zone arises in the well and the capacitor has a high ESD strength. An optionally present auxiliary doping layer ensures a high area capacitance of the capacitor despite high ESD strength.
Claims
9 · 2 independent · depth 3Classifications
3 codes- H01L23/62
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1 priority documents›Priority documents — 1
| Type | Document | Date |
|---|---|---|
| related publication | US 20090283810 A1 | 19 Nov 2009 |
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