A co-integrated HBT/FET apparatus and system, and methods for making the same, are disclosed. A co-integrated HBT/FET apparatus may include a first epitaxial structure formed over a substrate, the first epitaxial structure forming, at least in part, a FET device, a separation layer formed over the first epitaxial structure, and a second epitaxial structure formed over the separation layer, the second epitaxial structure forming, at least in part, a heterojunction bipolar transistor (HBT) device.

Claims

9 · 1 independent · depth 3

9 granted claims

›1.independentAn apparatus comprising:na first epitaxial structure formed over a substrate, the first epitaxial structure forming, at least in part, a field effect …+8

›2.↳ 1The apparatus of claim 1, wherein the separation layer comprises an etch stop layer comprising aluminum gallium arsenide (AlGaAs) or indium gallium ph…d2

›3.↳ 1The apparatus of claim 1, wherein the FET device is a pseudo-morphic high electron mobility transistor (pHEMT) device or a metal-semiconductor field e…d2

›4.↳ 1The apparatus of claim 1, wherein the FET device is an enhancement mode FET or a depletion mode FET device.d2+1

›6.↳ 1The apparatus of claim 1, wherein the substrate comprises a selected one of gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP).d2

›7.↳ 1The apparatus of claim 1, wherein the first epitaxial layer includes an implanted isolation region.d2+1

›9.↳ 1The apparatus of claim 1, wherein the collector contacts are disposed over the separation layer.d2

Classifications

6 codes

IPC · International Patent Classification

Section H — Electricity

H01L29/66

USPC · US Patent Classification

257/195257/E29.218257/192257/E29.171257/197

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Priority

7 Mar 2007

earliest claimed

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Type	Document	Date
provisional	US 60893412	7 Mar 2007

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