A gate of a semiconductor device includes a substrate, and a polysilicon layer over the substrate, wherein the polysilicon layer is doped with first conductive type impurities having a concentration that decreases when receding from the substrate and counter-doped with second conductive type impurities having a concentration that increases when receding from the substrate.

Claims

33 · 4 independent · depth 3

33 granted claims

›1.independentA gate of a semiconductor device comprising:na substrate; anda polysilicon layer over the substrate, which is doped with first conductive type impurit…+3

›5.independentA dual polysilicon gate of a semiconductor device, comprising:na substrate having a first region and a second region;a first polysilicon layer doped w…+4

›10.independentA method of fabricating a gate of a semiconductor device, comprising:nforming a polysilicon layer over a substrate, the polysilicon layer being doped …+11

›11.↳ 10The method of claim 10, wherein the first conductive type impurities include N type impurities, and the second conductive type impurities include P ty…d2

›12.↳ 10The method of claim 10, wherein the first conductive impurities include P type impurities, and the second conductive type impurities include N type im…d2

›13.↳ 10The method of claim 10, wherein the first conductive type impurities are in-situ doped.d2

›14.↳ 10The method of claim 10, wherein the first conductive type impurities have a stepped concentration distribution of multiple steps based on a depth in t…d2+1

›16.↳ 10The method of claim 10, wherein the first conductive type impurities have a concentration distribution of 8Ã—1020 atoms/cm3 to 1Ã—1020 atoms/cm3 in th…d2

›17.↳ 10The method of claim 10, wherein the counter doping is performed through Beam Line Implant or Plasma Doping.d2

›18.↳ 10The method of claim 10, wherein the counter doping is performed with a dose of 5Ã—1015 atoms/cm3 to 5Ã—1017 atoms/cm3.d2

›19.↳ 10The method of claim 10, wherein the counter doping is performed at energy of 0.1 keV to 10 keV.d2

›20.↳ 10The method of claim 10, wherein activating is performed using a rapid thermal process.d2

›21.↳ 10The method of claim 10, wherein the second conductive type impurities have a concentration increasing when receding from the substrate.d2

›22.independentA method of fabricating a dual polysilicon gate in a semiconductor device, comprising:nforming a first polysilicon layer over a substrate having a fir…+11

›23.↳ 22The method of claim 22, wherein the first conductive type impurities include N type impurities if the first region is NMOS, and the second conductive …d2

›24.↳ 22The method of claim 22, wherein the first conductive type impurities include P type impurities if the first region is PMOS, and the second conductive …d2

›25.↳ 22The method of claim 22, wherein the first conductive type impurities are in-situ doped.d2

›26.↳ 22The method of claim 22, wherein the first conductive type impurities have a stepped concentration distribution of multiple steps based on a depth from…d2+1

›28.↳ 22The method of claim 22, wherein the first conductive type impurities have a concentration distribution of 8Ã—1020 atoms/cm3 to 1Ã—1020 atoms/cm3 in th…d2

›29.↳ 22The method of claim 22, wherein the counter doping is performed through Beam Line Implant or Plasma Doping.d2

›30.↳ 22The method of claim 22, wherein the counter doping is performed with a dose of 5Ã—1015 atoms/cm3 to 5Ã—1017 atoms/cm3.d2

›31.↳ 22The method of claim 22, wherein the counter doping is performed at energy of 0.1 keV to 10 keV.d2

›32.↳ 22The method of claim 22, wherein the activation is performed using a rapid thermal process.d2

›33.↳ 22The method of claim 22, wherein the second conductive type impurities have a concentration increasing when receding from the substrate.d2

Classifications

11 codes

IPC · International Patent Classification

Section H — Electricity

H01L29/78
H01L21/425

USPC · US Patent Classification

257/412438/530438/587257/E21.294257/E21.336257/E29.255257/E21.473257/413438/585

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Type	Document	Date
related publication	US 20100084720 A1	8 Apr 2010

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