A method for making a nitride read only memory device with buried diffusion spacers is disclosed. An oxide-nitride-oxide (ONO) layer is formed on top of a silicon substrate, and a polysilicon gate is formed over the ONO layer. The polysilicon gate is formed less than a length of the ONO layer. Two buried diffusion spacers are formed beside two sidewalls of the polysilicon gate and over the ONO layer. Two buried diffusion regions are implanted on the silicon substrate next to the two buried diffusion spacers. The two buried diffusion regions are then annealed such that the approximate interfaces of the buried diffusion regions are under the sidewalls of the polysilicon gate. The structure of a nitride read only memory device with buried diffusion spacers is also described.

Claims

14 · 1 independent · depth 5

14 granted claims

›1.independentA method for making a memory, comprising:nproviding a substrate;forming a first polysilicon gate and a portion of a second polysilicon gate over the s…+13

›2.↳ 1The method for making a memory as recited in claim 1, further comprising: forming first and second oxide regions respectively beside and between the f…d2+1

›4.↳ 1The method for making a memory as recited in claim 1, wherein forming the first and second insulator spacers is performed by depositing a conformal in…d2

›5.↳ 1The method for making a memory as recited in claim 1, wherein forming the first and second buried diffusion regions is performed by a buried diffusion…d2

›6.↳ 1The method for making a memory as recited in claim 1, wherein annealing the first and second buried diffusion regions is performed by a rapid thermal …d2

›7.↳ 1The method for making a memory as recited in claim 1, wherein forming the first polysilicon gate is performed by depositing a polysilicon layer on the…d2

›8.↳ 1The method for making a memory as recited in claim 1, wherein each of the first and second insulator spacers is defined by a type of oxide.d2

›9.↳ 1The method for making a memory as recited in claim 1, wherein making the memory can be integrated with making a periphery device by dividing the subst…d2+5

Classifications

10 codes

IPC · International Patent Classification

Section H — Electricity

H01L21/336

USPC · US Patent Classification

438/287438/199257/369438/224257/E21.423257/51438/408257/75438/487

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Pendency

2.0 y

730 days filing → grant

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non-final + final

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2 RCE

Examiner

Wilner Jean Baptiste

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20090246925 A1	1 Oct 2009

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