In a semiconductor integrated circuit, power source wiring for supplying power supply voltage to a plurality of flip flop circuits, and power source wiring for supplying different power supply voltage to a combinational circuit are provided individually, so that the power supply to the flip flop circuits and the power supply to the combinational circuit can be performed separately from, and independently of, each other. During shift operation in scan testing, the power supply voltage to the combinational circuit is set to a low voltage or cut off, thereby suppressing the amount of power consumed by the combinational circuit portion during the shift operation. At the same time, the power supply voltage to the flip flop circuits is set to a high voltage during the shift operation.

Claims

23 · 3 independent · depth 3

23 granted claims

›1.independentA semiconductor integrated circuit comprising:na combinational circuit connected with a plurality of flip flop circuits;the plurality of flip flop cir…+11

›3.↳ 1The circuit of claim 1, further comprising a variable power supply circuit for varying the first power supply voltage to the flip-flop-circuit power s…d2+1

›4.↳ 1The circuit of claim 1, wherein during capture operation in which the output signals from the combinational circuit are captured into the plurality of…d2

›5.↳ 1The circuit of claim 1, wherein during capture operation in which the output signals from the combinational circuit are captured into the plurality of…d2

›6.↳ 1multiple · 1, 2The circuit of claim 1 or 2, further comprising a built-in self-test device for performing a self-test of the combinational circuit.d2

›8.↳ 1The circuit of claim 1, further comprising:na first region, in which a plurality of flip-flop-circuit standard cells are provided;a second region, in …d2+1

›11.↳ 1The circuit of claim 1, further comprising a plurality of standard cells, each of which includes therein:na first power source wiring for supplying po…d2

›12.↳ 1A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of claim 1, the method comprising:nthe first step o…d2+1

›16.↳ 1A semiconductor integrated circuit testing method for testing the semiconductor integrated circuit of claim 1, the method comprising:nthe first step o…d2

›2.independentA semiconductor integrated circuit comprising:na combinational circuit connected with a plurality of flip flop circuits;the plurality of flip flop cir…+4

›7.↳ 2The circuit of claim 2, further comprising:na measuring circuit for measuring a period of restoring time required for variation in the power supply vo…d2+2

›10.↳ 2The circuit of claim 2, further comprisingna combinational-circuit standard cell which includes a power source cut-off circuit.d2

›18.independentA semiconductor integrated circuit comprising;na combinational circuit connected with a plurality of flip flop circuits;the plurality of flip flop cir…+5

›19.↳ 18The circuit of claim 18, further comprising a variable power supply circuit for varying the first power supply voltage to the flip-flop-circuit power …d2

›20.↳ 18The circuit of claim 18, wherein during capture operation in which the output signals from the combinational circuit are captured into the plurality o…d2

›21.↳ 18The circuit of claim 18, wherein during capture operation in which the output signals from the combinational circuit are captured into the plurality o…d2

›22.↳ 18The circuit of claim 18, further comprising a built-in self-test device for performing a self-test of the combinational circuit.d2

›23.↳ 18The circuit of claim 18, further comprising:na measuring circuit for measuring a period of restoring time required for variation in the first power su…d2

Classifications

10 codes

IPC · International Patent Classification

Section G — Physics

G06F11/00
G06F1/26
G06F1/00
G01R31/28

USPC · US Patent Classification

714/726713/324714/729713/340714/30713/320

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3.4 y

1,243 days filing → grant

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non-final + final

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Cynthia Britt

art unit 2117 · TC 2100

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1 priority documents

›Priority documents — 1

Type	Document	Date
related publication	US 20060174176 A1	3 Aug 2006

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