USPatentGranted
B2

Manufacturing method of semiconductor device

Granted 25 Apr 2006 · 2 office actions

Current assignee: Semiconductor Energy Laboratory Co., Ltd. · originally Semiconductor Energy Laboratory

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Inventors: Ichiro Uehara, Hideomi Suzawa · Examiner: Phuc T. Dang · AU 2818 · TC 2800

Life of the patent

8 dated events
⤢ drag to zoom20042006200820102012201420162018202020222024ProsecutionTerm & fees
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Abstract

In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of L ov area to a desired dimensional range so that the dimension thereof becomes larger.

Claims

20 · 3 independent · depth 2
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20 granted claims

Classifications

4 codes
IPC · International Patent Classification
Section H — Electricity
  • H01L21/302
  • H01L21/461
USPC · US Patent Classification
438/713438/749

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File wrapper

⤢ drag to zoomApr 2004Jul 2004Oct 2004Jan 2005Apr 2005Jul 2005Oct 2005Jan 2006Apr 2006USPTOApplicantNon-final rejectionResponse after non-finalNotice of allowance
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Pendency
1.9 y
701 days filing → grant
Office actions
1
non-final + final
Responses
4
no RCE
Examiner
Phuc T. Dang
art unit 2818 · TC 2800
Citations: 6 back · 0 forward

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Term & fees

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Priority chain

1 priority documents
›Priority documents — 1
TypeDocumentDate
related publicationUS 20040224514 A111 Nov 2004

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Citations

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