Manufacturing method of semiconductor device
Granted 25 Apr 2006 · 2 office actions
Current assignee: Semiconductor Energy Laboratory Co., Ltd. · originally Semiconductor Energy Laboratory
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Inventors: Ichiro Uehara, Hideomi Suzawa · Examiner: Phuc T. Dang · AU 2818 · TC 2800
Life of the patent
8 dated eventsAbstract
In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist, which contains a photo-absorbent of diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of L ov area to a desired dimensional range so that the dimension thereof becomes larger.
Claims
20 · 3 independent · depth 2Classifications
4 codes- H01L21/302
- H01L21/461
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1 priority documents›Priority documents — 1
| Type | Document | Date |
|---|---|---|
| related publication | US 20040224514 A1 | 11 Nov 2004 |
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