An insulated-gate field-effect transistor adapted to be used in an active-matrix liquid-crystal display. The channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Classifications

5 codes

IPC · International Patent Classification

Section H — Electricity

H01L3/1039

USPC · US Patent Classification

257/59257/408257/344257/72

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Pendency

1.4 y

518 days filing → grant

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Allan R. Wilson

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1 priority documents

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Type	Document	Date
related publication	US 20030173570 A1	18 Sep 2003

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