Apparatus for generating high voltage signal

The present invention relates to a semiconductor memory device; and, more particularly, to a high voltage generator for providing a high voltage signal for compensating a threshold voltage loss in a semiconductor memory device.

In a typical semiconductor memory device, a high voltage generator is used for compensating a voltage loss caused due to threshold voltages of metal oxide semiconductor (MOS) transistors. The high voltage generator supplies a high voltage signal that has a voltage level higher than an external power signal.

Since the high voltage signal can compensates for the threshold voltage loss, the high voltage generator are widely used in a word line drive circuit, a bit line isolation circuit, a data output buffer circuit, and the like.

FIG. 1 is a block diagram showing a conventional high voltage generator, and FIG. 2 shows a timing chart of the conventional high generator shown in FIG. 1 .

Referring to FIGS. 1 and 2, a conventional high voltage generator 100 includes a level detection unit 110 , an oscillation unit 130 and a high-voltage charge pump unit 150 .

The level detection unit 110 detects a voltage level of a high voltage signal VPP to generate a high voltage enable signal PPEN when the voltage level of the high voltage signal VPP reaches a predetermined target value.

The oscillation unit 130 periodically generates an oscillation signal OSC in response to the high voltage enable signal PPEN.

The high-voltage charge pump unit 150 performs a pumping operation in response to the oscillation signal OSC to increase a voltage level of the external power signal VEXT, to thereby generate the high voltage signal VPP. Here, the high voltage signal VPP is fed back to the level detection unit 110 .

At this time, the high-voltage charge pump unit 150 is generally implemented with a plurality of cross-coupled NMOS transistors and a transfer transistor for transferring a voltage level of (VPP+VDD), where VDD is a power potential applied to the pulse generator 100 . However, a maximum gate potential of the transfer transistor reaches 3 VDD, which corresponds to about (VPP+VDD), so that a reliability related to gate oxide layers and a junction breakdown is deteriorated.

It is, therefore, an object of the present invention to provide a high voltage generator including a high-voltage charge pump unit, in which reliability related to the gate oxide layers and the junction breakdown is improved by reducing the maximum gate potential of the high-voltage charge pump unit to twice the power potential (2 VDD).

In accordance with an aspect of the present invention, there is provided a high-voltage charge pump circuit for use in a semiconductor memory device, comprising: a precharge control means for precharging a first and a second nodes to a power potential in response to a first and a second clocks, respectively; a precharge means for precharging a third and a fourth nodes to the power potential in response to voltage levels of the first and second nodes, respectively; a first charge pumping means for bootstrapping the first and the second nodes to twice the power potential in response to the first and the second clocks, respectively; a second charge pumping means for bootstrapping the third and the fourth bootstrapping nodes to twice the power potential in response to a third and a fourth clocks; and a transfer means for transferring voltage level of the third and the fourth nodes to an exterior in response to voltage levels of the fourth and the third nodes, respectively.

In accordance with another aspect of the present invention, there is provided a high voltage generator for providing a high voltage signal for use in a semiconductor memory device, comprising: a level detection means for detecting a voltage level of the high voltage signal to generate a high voltage enable signal when the voltage level of the high voltage signal reaches a predetermined target value; an oscillation means, in response to the high voltage enable signal, for generating a plurality of clocks, the clocks including a first to a fourth clocks; a high-voltage charge pump means, in response to the clocks, for increasing a voltage level of an external power signal to generate the high voltage signal to a high voltage node; and a power-on precharging means, in response to a control signal, for initializing the high voltage node to a predetermined level.

Other objects and aspects of the invention will become apparent from the following description of the embodiments with reference to the accompanying drawings, in which:

FIG. 1 is a block diagram showing a conventional high voltage generator;

FIG. 2 shows a timing chart of the conventional high generator shown in FIG. 1;

FIG. 3 is a block diagram illustrating a high voltage generator in accordance with an embodiment of the present invention;

FIG. 4 is a circuit diagram illustrating a high-voltage charge pump unit shown in FIG. 3;

FIG. 5 is a table illustrating each voltage level of bootstrapping nodes in the high-voltage charge pump unit shown in FIG. 4 according to clocks;

FIG. 6 is a timing chart of each bootstrapping node in FIG. 4; and

FIG. 7 is a circuit diagram illustrating a power-on precharge unit shown in FIG. 3 .

FIG. 3 is a block diagram illustrating a high voltage generator in accordance with the present invention.

Referring to FIG. 3, the high voltage generator 300 in accordance with the present invention includes a level detection unit 310 , an oscillation unit 320 , a high-voltage charge pump unit 330 and a power-on precharge unit 340 .

The level detection unit 310 detects a voltage level of a high voltage signal VPP to generate a high voltage enable signal PPEN when the voltage level of the high voltage signal VPP reaches a predetermined target value.

The oscillation unit 320 periodically generates an oscillation signal OSC in response to the high voltage enable signal PPEN. The oscillation signal OSC includes a first to a fourth clocks.

The high-voltage charge pump unit 330 performs a pumping operation in response to the oscillation signal OSC to increase a voltage level of the external power signal VEXT to thereby generate the high voltage signal VPP to a high voltage node NP. Here, the high voltage signal VPP is fed back to the level detection unit 310 .

The power-on precharge unit 340 initializes the high voltage node NP to a predetermined voltage level in response to a power-on signal/PWRON, which is activated when a power applied to the high voltage generator 300 is on. That is, before the high-voltage charge pump unit 330 performs the pumping operation, the high voltage node NP is initialized to a voltage of (VEXT−VTH), where VTH is a threshold voltage of NMOS transistors contained in the high-voltage charge pump unit 330 .

FIG. 4 is a circuit diagram illustrating the high-voltage charge pump unit 330 shown in FIG. 3 .

Referring to FIG. 4, the high-voltage charge pump unit 330 includes a precharge control block 410 , a precharge block 420 , a first charge pump block 430 , a second charge pump block 440 and a transfer block 450 .

The precharge control block 410 precharges a first and a second bootstrapping nodes N 41 and N 42 to a power potential VDD when a first and a second clocks CLK 41 and CLK 42 are the power potential VDD.

The precharge block 420 precharges a third and a fourth bootstrapping nodes N 43 and N 44 to the power potential VDD in response to voltage levels of the first and the second bootstrapping nodes N 41 and N 42 .

The first charge pump block 430 bootstraps the first and the second bootstrapping nodes N 41 and N 42 to a voltage level of 2 VDD in response to the first and the second clocks CLK 41 and CLK 42 .

The second charge pump block 440 bootstraps the third and the fourth bootstrapping nodes N 43 and N 44 to a voltage level of 2 VDD in response to a third and a fourth clock CLK 43 and CLK 44 .

The transfer block 450 transfers each voltage level of the third and the fourth bootstrapping nodes N 43 and N 44 to the high voltage node NP in response to each voltage level of the fourth and the third bootstrapping nodes N 44 and N 43 , respectively.

The precharge control block 410 includes: a PMOS transistor MP 43 having a source coupled to the power potential VDD and a gate coupled to a fifth bootstrapping node N 45 ; a PMOS transistor MP 45 having a source coupled to a drain of the PMOS transistor MP 43 , a drain coupled to the fifth bootstrapping node N 45 and a gate receiving the first clock CLK 41 ; an NMOS transistor MN 47 having a drain coupled to the drain of the PMOS transistor MP 45 , a source coupled to a ground potential GND and a gate receiving the first clock CLK 41 ; a PMOS transistor MP 44 having a source coupled to the power potential VDD and a gate coupled to a sixth bootstrapping node N 46 ; a PMOS transistor MP 46 having a source coupled to a drain of the PMOS transistor MP 44 , a drain coupled to the sixth bootstrapping node N 46 and a gate receiving the second clock CLK 42 ; and an NMOS transistor MN 48 having a drain coupled to the drain of the PMOS transistor MP 46 , a source coupled to the ground potential GND and a gate receiving the second clock CLK 42 .

In the precharge control block 410 , when the first clock CLK 41 is a low level, the PMOS transistor MP 45 transfers a voltage level of the second bootstrapping node N 42 to the fifth bootstrapping node N 45 . When the first clock CLK 41 is a high level, the fifth bootstrapping node N 45 is set to the ground potential through the NMOS transistor MN 47 . In similar manner, when the second clock CLK 42 is a low level, the PMOS transistor MP 46 transfers a voltage level of the first bootstrapping node N 41 to the sixth bootstrapping node N 46 . When the second clock CLK 42 is a high level, the sixth bootstrapping node N 46 is set to the ground potential through the NMOS transistor MN 48 .

The precharge block 420 includes an NMOS transistor MN 45 , coupled between the power potential VDD and the third bootstrapping node N 43 , whose gate receives a voltage level of the first bootstrapping node N 41 , and an NMOS transistor MN 46 , coupled between the power potential VDD and the fourth bootstrapping node N 44 , whose gate receives a voltage level of the second bootstrapping node N 42 .

The first charge pump block 430 includes an NMOS transistor MN 41 having a drain and a source receiving the first clock CLK 41 and a gate coupled to the first bootstrapping node N 41 , and an NMOS transistor MN 42 having a drain and a source receiving the second clock CLK 42 and a gate coupled to the second bootstrapping node N 42 .

The second charge pump block 440 includes an NMOS transistor MN 43 having a drain and a source receiving the third clock CLK 43 and a gate coupled to the third bootstrapping node N 43 , and an NMOS transistor MN 44 having a drain and a source receiving the fourth clock CLK 44 and a gate coupled to the fourth bootstrapping node N 44 .

The transfer block 450 includes a PMOS transistor MP 41 , coupled between the third bootstrapping node N 43 and the high voltage node NP, whose gate receives a voltage level of the fourth bootstrapping node N 44 , and a PMOS transistor MP 42 , coupled between the fourth bootstrapping node N 44 and the high voltage node NP, whose gate receives a voltage level of the third bootstrapping node N 43 .

At this time, the second clock CLK 42 and the third clock CLK 43 has the same phase except for non-overlapping times, and the first clock CLK 41 and the fourth clock CLK 44 has the same phase.

FIG. 5 is a table illustrating each voltage level of the bootstrapping nodes N 41 to N 46 in the high-voltage charge pump unit 330 , shown in FIG. 4, according to the clocks CLK 41 to CLK 44 , and FIG. 6 is a timing chart of each bootstrapping node in FIG. 4 .

Referring to FIGS. 5 and 6, steady-state voltages of the first and second bootstrapping nodes N 41 and N 42 swing in a range of VDD to 2 VDD by the precharge control block 410 . Therefore, while the maximum gate potential of NMOS transistor in the prior art is (VPP+2 VDD), the maximum gate potential of the NMOS transistors MN 45 and MN 46 according to the present invention is 2 VDD with respect to P-substrate.

During a time period denoted by t 1 in FIG. 6, positive pumping charges of the fourth bootstrapping node N 44 are transferred to the high voltage node NP through the PMOS transistor MP 42 .

Also, during a time period denoted by t 5 in FIG. 6, the voltage levels of the first to the fourth clocks CLK 41 , CLK 42 , CLK 43 and CLK 44 are VDD, 0V, 0V and VDD, respectively. Since the voltage levels of the first and the second bootstrapping nodes N 41 and N 42 are VDD and 2 VDD, respectively, the fourth bootstrapping node N 44 is precharged to VDD through the NMOS transistor MN 46 , and the NMOS transistor MN 45 is turned off.

As a result, the voltage levels of the third and the fourth bootstrapping nodes N 43 and N 44 become VPP and VDD respectively, and positive pumping charges of the third bootstrapping node N 43 are fully transferred to the high voltage node NP through the PMOS transistor MP 41 .

Therefore, the charge pumping occurs twice in one cycle time as shown in FIG. 6 . This is called two-phase charge pumping.

For obtaining a proper operation of the high-voltage charge pump unit 330 , the NMOS transistor MN 45 must be turned on when a potential applied to the gate of the NMOS transistor MN 45 is 2 VDD. Since a potential applied to the source of the NMOS transistor MN 45 is VDD, a potential between the gate and the source must be greater than the threshold voltage of the NMOS transistor MN 45 .

FIG. 7 is a circuit diagram illustrating the power-on precharge unit 340 shown in FIG. 3 .

Referring to FIG. 7, the power-on precharge unit 340 includes: a PMOS transistor MP 71 coupled between the power potential and the high voltage node Np; a PMOS transistor MP 72 having a source coupled to a drain of the PMOS transistor MP 71 and a gate receiving the power-on signal/PWRON; and an NMOS transistor MN 71 having a drain coupled to a drain of the PMOS transistor MP 72 , a source coupled to the ground potential GND and a gate receiving the power-on signal/PWRON. Furthermore, a gate of the PMOS transistor MP 71 is coupled to the drain of the NMOS transistor MN 71 .

During a power-on period, i.e., when the power-on signal/PWRON remains at the power potential VDD, the PMOS transistor MP 72 is turned off, and the NMOS transistor MN 71 and the PMOS transistor MP 71 are turned on. As a result, the power-on precharge unit 340 precharges the high voltage node NP to the power potential VDD.

Then, when the power-on signal/PWRON is changed to 0V, the NMOS transistor MN 71 is turned off. Also, the PMOS transistor MP 72 is turned on and the PMOS transistor MP 71 is turned off. As a result, the high voltage node NP is increased toward the target value by the high-voltage charge pump unit 330 .

As described above, by reducing the maximum gate potential of the high-voltage charge pump unit to 2 VDD, the reliability related to the gate oxide and the breakdown of the junction diodes is improved. Additionally, instead of (VDD−VTH), the high voltage node is precharged by the power potential VDD, thereby reducing a setting time of the high voltage signal.

Although the preferred embodiments of the invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.