›1.independentAn active matrix device comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors formed with said se…+2
An active matrix device comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors including source, drain and channel regions formed in said semiconductor layer, and a gate electrode adjacent to said channel forming region; a pixel electrode formed over said substrate; a signal line formed over said substrate, electrically connected to said pixel electrode through said first and second thin film transistors in series; a capacitor forming electrode and a portion of said semiconductor layer and an insulating film interposed therebetween, wherein said portion of the semiconductor layer is disposed between a pair of impurity regions in said semiconductor layer, and said impurity regions have a same conductivity type as the source and drain regions of said first and second thin film transistors.
›2.↳ 1The active matrix device according to claim 1 wherein said portion of the semiconductor layer has a same conductivity type as said channel region.d2
The active matrix device according to claim 1 wherein said portion of the semiconductor layer has a same conductivity type as said channel region.
›3.↳ 1The active matrix device according to claim 1 wherein said semiconductor layer comprises crystalline silicon.d2
The active matrix device according to claim 1 wherein said semiconductor layer comprises crystalline silicon.
›4.independentAn active matrix device comprising: a gate wiring including at least first and second gate electrodes formed over a substrate; a signal line formed ov…+1
An active matrix device comprising: a gate wiring including at least first and second gate electrodes formed over a substrate; a signal line formed over said substrate; a pixel electrode formed over said substrate; a semiconductor layer formed over said substrate and adjacent to said at least first and second gate electrodes; a first channel region and a second channel region formed in said semiconductor layer adjacent to said first gate electrode and said second gate electrode, respectively; a first impurity region formed in said semiconductor layer wherein said first impurity region is connected to said signal line; a second impurity region formed in said semiconductor layer wherein said second impurity region has a same conductivity type as said first impurity region and extends between said first and second channel regions; a third impurity region formed in said semiconductor layer wherein said third impurity region has a same conductivity type as said first impurity region and is connected to said pixel electrode; a capacitor forming electrode adjacent to a portion of said semiconductor layer wherein said portion of the semiconductor layer has a same conductivity type as said first and second channel regions; a fourth impurity region formed in said semiconductor layer and having a same conductivity type as said first impurity region wherein said portion of the semiconductor layer extends between said third impurity region and said fourth impurity region; a capacitor comprising said capacitor forming electrode and said portion of the semiconductor layer with an insulating film interposed therebetween.
›5.↳ 4The active matrix device according to claim 4 wherein said semiconductor layer comprises crystalline silicon.d2
The active matrix device according to claim 4 wherein said semiconductor layer comprises crystalline silicon.
›6.independentAn active matrix device comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors of a same channel c…+1
An active matrix device comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors of a same channel conductivity type formed with said semiconductor layer, each of said first and second thin film transistors including source, drain and channel regions formed in said semiconductor layer, and a gate electrode adjacent to said channel forming region; a pixel electrode formed over said substrate; a signal line formed over said substrate, electrically connected to said pixel electrode through said first and second thin film transistors in series; a first capacitor comprising a capacitor forming electrode and a portion of said semiconductor layer and a first insulating film interposed therebetween; and a second capacitor comprising said capacitor forming electrode and said pixel electrode with a second insulating film interposed therebetween; wherein said portion of the semiconductor layer is disposed between a pair of impurity regions in said semiconductor layer, and said impurity regions have a same conductivity type as the source and drain regions of said first and second thin film transistors.
›7.↳ 6The active matrix device according to claim 6 wherein said semiconductor layer comprises crystalline silicon.d2
The active matrix device according to claim 6 wherein said semiconductor layer comprises crystalline silicon.
›8.independentAn active matrix device comprising having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said activ…+1
An active matrix device comprising having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said active matrix circuit comprising: a pixel electrode formed over a substrate; a capacitor forming electrode formed between said substrate and said pixel electrode; at least two thin film transistors connected to said pixel electrode in series, each of thin film transistors comprising a semiconductor layer comprising at least a channel forming region and source and drain regions, and a gate electrode provided adjacent to said semiconductor layer with an insulating film interposed therebetween; a gate line connected to each of said gate electrodes of said thin film transistors; a signal line connected to one of said source regions of said thin film transistors connected in series, wherein an auxiliary capacitor is formed between said semiconductor layer and said capacitor forming electrode; (b) said driver circuit comprising: a CMOS device comprising a pair of a P-channel thin film transistor and an N-channel thin film transistor formed over said substrate, wherein source and drain regions of one of said P-channel thin film transistor and said N-channel thin film transistor are doped with a first impurity and source and drain regions of the other one of said P-channel thin fill transistor and said N-channel thin film transistor are doped with both said first impurity and a second impurity having an opposite conductivity type to said first impurity.
›9.↳ 8The active matrix device according to claim 8 wherein said semiconductor layer comprises crystalline silicon.d2
The active matrix device according to claim 8 wherein said semiconductor layer comprises crystalline silicon.
›10.independentAn active matrix device comprising having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said activ…+1
An active matrix device comprising having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said active matrix circuit comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors formed with said semiconductor layer, each of which includes a channel forming region in said semiconductor layer and a gate electrode adjacent to said channel forming region; a pixel electrode formed over said substrate; a signal line formed over said substrate, electrically connected to said pixel electrode through said first and second thin film transistors in series; a capacitor forming electrode formed adjacent to a portion of said semiconductor layer to form a capacitor therebetween, wherein said portion of said semiconductor layer has a same conductivity type as said channel forming region; (b) said driver circuit comprising: a CMOS device comprising a pair of a P-channel thin film transistor and an N-channel thin film transistor formed over said substrate, wherein source and drain regions of one of said P-channel thin film transistor and said N-channel thin film transistor are doped with a first impurity and source and drain regions of the other one of said P-channel thin film transistor and said N-channel thin film transistor are doped with both said first impurity and a second impurity having an opposite conductivity type to said first impurity.
›11.↳ 10The active matrix device according to claim 10 wherein said semiconductor layer comprises crystalline silicon.d2
The active matrix device according to claim 10 wherein said semiconductor layer comprises crystalline silicon.
›12.independentAn active matrix device comprising having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said activ…+1
An active matrix device comprising having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said active matrix circuit comprising: a pixel electrode formed over a substrate; a capacitor forming electrode formed between said substrate and said pixel electrode; at least two thin film transistors connected to said pixel electrode in series, each thin film transistors comprising a semiconductor layer comprising at least a channel forming region, source and drain regions, and a gate electrode provided adjacent to said semiconductor layer with an insulating film interposed therebetween; a gate line connected to each of said gate electrodes of said thin film transistors; a signal line connected to one of said source regions of said thin film transistors connected in series, wherein a first capacitor is formed between said semiconductor layer and said capacitor forming electrode and a second capacitor is formed between said capacitor forming electrode and said pixel electrode; (b) said driver circuit comprising: a CMOS device comprising a pair of a P-channel thin film transistor and an N-channel thin film transistor formed over said substrate, wherein source and drain regions of one of said P-channel thin film transistor and said N-channel thin film transistor are doped with a first impurity and source and drain regions of the other one of said P-channel thin film transistor and said N-channel thin film transistor are doped with both said first impurity and a second impurity having an opposite conductivity type to said first impurity.
›13.↳ 12The active matrix device according to claim 12 wherein said semiconductor layer comprises crystalline silicon.d2
The active matrix device according to claim 12 wherein said semiconductor layer comprises crystalline silicon.
›14.independentAn active matrix device comprising having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said activ…
An active matrix device comprising having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said active matrix circuit comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors of a same channel conductivity type formed with said semiconductor layer, each of said first and second thin film transistors including source, drain and channel regions formed in said semiconductor layer, and a gate electrode adjacent to said channel forming region; a pixel electrode formed over said substrate; a signal line formed over said substrate, electrically connected to said pixel electrode through said first and second thin film transistors in series; a first capacitor comprising a capacitor forming electrode and a portion of said semiconductor layer and a first insulating film interposed therebetween; and a second capacitor comprising said capacitor forming electrode and said pixel electrode with a second insulating film interposed therebetween; wherein said portion of the semiconductor layer is disposed between a pair of impurity regions in said semiconductor layer, and said impurity regions have a same conductivity type as the source and drain regions of said first and second thin film transistors; (b) said driver circuit comprising: a CMOS device comprising a pair of a P-channel thin film transistor and an N-channel thin film transistor formed over said substrate, wherein source and drain regions of one of said P-channel thin film transistor and said N-channel thin film transistor are doped with a first impurity and source and drain regions of the other one of said P-channel in film transistor and said N-channel thin film transistor are doped with both said first impurity and a second impurity having an opposite conductivity type to said first impurity.
›15.independentA semiconductor device having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said active matrix cir…+6
A semiconductor device having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said active matrix circuit comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors including source, drain and channel regions formed in said semiconductor layer and a gate electrode adjacent to said channel forming region; and a pixel electrode connected to one of said first and second thin film transistors, (b) said driver circuit comprising: at least one CMOS device comprising a pair of a P-channel and N channel thin film transistors formed over said substrate, said N-channel thin film transistor having at least one LDD region.
›16.↳ 15The device according to claim 15 wherein said semiconductor layer comprises crystalline silicon.d2
The device according to claim 15 wherein said semiconductor layer comprises crystalline silicon.
›17.↳ 15The device according to claim 15 wherein said semiconductor layer has a thickness of 400 through 1000 .ANG..d2
The device according to claim 15 wherein said semiconductor layer has a thickness of 400 through 1000 .ANG..
›18.↳ 15The device according to claim 15 further comprising a capacitor forming electrode formed over said substrate.d2+2
The device according to claim 15 further comprising a capacitor forming electrode formed over said substrate.
›19.↳ 18The device according to claim 18 wherein an auxiliary capacitor is formed between said pixel electrode and said capacitor forming electrode with an in…d3
The device according to claim 18 wherein an auxiliary capacitor is formed between said pixel electrode and said capacitor forming electrode with an interlayer insulating film therebetween.
›20.↳ 18The device according to claim 18 wherein said capacitor forming electrode is kept at a constant voltage.d3
The device according to claim 18 wherein said capacitor forming electrode is kept at a constant voltage.
›21.↳ 15The device according to claim 15 wherein said gate electrode is located over said semiconductor layer.d2
The device according to claim 15 wherein said gate electrode is located over said semiconductor layer.
›22.independentA semiconductor device having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, a) said active matrix circ…+5
A semiconductor device having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, a) said active matrix circuit comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors including source, drain and channel regions formed in said semiconductor layer and a gate electrode adjacent to said channel forming region; a pixel electrode connected to one of said first and second thin film transistors; and a capacitor formed between a portion of said semiconductor layer and a capacitor forming electrode, wherein said portion of the semiconductor layer has a same conductivity type as said channel forming region, (b) said driver circuit comprising: at least one CMOS device formed over said substrate, said CMOS device comprising a pair of P-channel and N-channel thin film transistors, said N-channel thin film transistor having at least one LDD region.
›23.↳ 22The device according to claim 22 wherein said semiconductor layer comprises crystalline silicon.d2
The device according to claim 22 wherein said semiconductor layer comprises crystalline silicon.
›24.↳ 22The device according to claim 22 wherein said semiconductor layer has a thickness of 400 through 1000 .ANG..d2
The device according to claim 22 wherein said semiconductor layer has a thickness of 400 through 1000 .ANG..
›25.↳ 22The device according to claim 22 further comprising an auxiliary capacitor formed between said pixel electrode and said capacitor forming electrode wi…d2
The device according to claim 22 further comprising an auxiliary capacitor formed between said pixel electrode and said capacitor forming electrode with an interlayer insulating film therebetween.
›26.↳ 22The device according to claim 22 wherein said capacitor forming electrode is kept at a constant voltage.d2
The device according to claim 22 wherein said capacitor forming electrode is kept at a constant voltage.
›27.↳ 22The device according to claim 22 wherein said gate electrode is located over said semiconductor layer.d2
The device according to claim 22 wherein said gate electrode is located over said semiconductor layer.
›28.independentA semiconductor device having at least an active matrix circuit and a driver for driving the active matrix circuit, (a) said active matrix circuit com…+5
A semiconductor device having at least an active matrix circuit and a driver for driving the active matrix circuit, (a) said active matrix circuit comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors including source, drain and channel regions formed in said semiconductor layer and a gate electrode adjacent to said channel forming region; a capacitor forming electrode formed over said substrate; and a pixel electrode connected to one of said first and second thin film transistors; a first capacitor formed between a portion of said semiconductor layer and said capacitor forming electrode; and a second capacitor between said capacitor forming electrode and said pixel electrode, wherein said portion of the semiconductor layer has a same conductivity type as the channel regions in said first and second thin film transistors, (b) said driver circuit comprising: at least one CMOS device comprising a pair of P-channel and N channel thin film transistors formed over said substrate, said N-channel thin film transistor having at least one LDD region.
›29.↳ 28The device according to claim 28 wherein said semiconductor layer comprises crystalline silicon.d2
The device according to claim 28 wherein said semiconductor layer comprises crystalline silicon.
›30.↳ 28The device according to claim 28 wherein said semiconductor layer has a thickness of 400 through 1000 .ANG..d2
The device according to claim 28 wherein said semiconductor layer has a thickness of 400 through 1000 .ANG..
›31.↳ 28The device according to claim 28 further comprising a first interlayer insulating film formed between said semiconductor layer and said capacitor form…d2
The device according to claim 28 further comprising a first interlayer insulating film formed between said semiconductor layer and said capacitor forming electrode, and a second interlayer insulating film formed between said capacitor forming electrode and said pixel electrode.
›32.↳ 28The device according to claim 28 wherein said capacitor forming electrode is kept at a constant voltage.d2
The device according to claim 28 wherein said capacitor forming electrode is kept at a constant voltage.
›33.↳ 28The device according to claim 28 wherein said gate electrode is located over said semiconductor layer.d2
The device according to claim 28 wherein said gate electrode is located over said semiconductor layer.
›34.independentA semiconductor device having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said active matrix cir…+5
A semiconductor device having at least an active matrix circuit and a driver circuit for driving the active matrix circuit, (a) said active matrix circuit comprising: a semiconductor layer formed over a substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors including source, drain and channel regions formed in said semiconductor layer, and a gate electrode adjacent to said channel forming region; a pixel electrode connected to one of said first and second thin film transistors; and a capacitor comprising a capacitor forming electrode and a portion of said semiconductor layer and an insulating film interposed therebetween, (b) said driver circuit comprising: at least one CMOS device comprising a pair of P-channel and N channel thin film transistors formed over said substrate, said N-channel thin film transistor having at least one LDD region, and said P-channel thin film transistor having no LDD region.
›35.↳ 34The device according to claim 34 wherein said semiconductor layer comprises crystalline silicon.d2
The device according to claim 34 wherein said semiconductor layer comprises crystalline silicon.
›36.↳ 34The device according to claim 34 wherein said semiconductor layer has a thickness of 400 through 1000 .ANG..d2
The device according to claim 34 wherein said semiconductor layer has a thickness of 400 through 1000 .ANG..
›37.↳ 34The device according to claim 34 further comprising an auxiliary capacitor formed between said pixel electrode and said capacitor forming electrode wi…d2
The device according to claim 34 further comprising an auxiliary capacitor formed between said pixel electrode and said capacitor forming electrode with an interlayer insulating film therebetween.
›38.↳ 34The device according to claim 34 wherein said capacitor forming electrode is kept at a constant voltage.d2
The device according to claim 34 wherein said capacitor forming electrode is kept at a constant voltage.
›39.↳ 34The device according to claim 34 wherein said gate electrode is located over said semiconductor layer.d2
The device according to claim 34 wherein said gate electrode is located over said semiconductor layer.
›40.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a metal layer formed over said substrate connected to one of said first and second thin film transistors, a peripheral driving circuit formed over said substrate comprising a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising a semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, and a passivation film formed over said first and second thin film transistors, and said CMOS circuit.
›41.↳ 40A device according to claim 40, wherein said semiconductor layer comprises crystalline silicon.d2
A device according to claim 40, wherein said semiconductor layer comprises crystalline silicon.
›42.↳ 40A device according to claim 40, wherein said passivation film comprises silicon nitride.d2
A device according to claim 40, wherein said passivation film comprises silicon nitride.
›43.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; and a metal layer formed over said substrate connected to one of said first and second thin film transistors, a peripheral driving circuit formed over said substrate comprising a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising a semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, wherein said N-channel thin film transistor has a LDD structure, and a passivation film formed over said first and second thin film transistors, and said CMOS circuit.
›44.↳ 43A device according to claim 43, wherein said semiconductor layer comprises crystalline silicon.d2
A device according to claim 43, wherein said semiconductor layer comprises crystalline silicon.
›45.↳ 43A device according to claim 43, wherein said passivation film comprises silicon nitride.d2
A device according to claim 43, wherein said passivation film comprises silicon nitride.
›46.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; an interlayer insulating film formed over said first and second thin film transistors; a metal layer connected to one of said first and second thin film transistors via said interlayer insulating film; passivation film formed over said interlayer insulating film and said metal layer; and a pixel electrode formed on said passivation film connected to the other one of said first and second thin film transistors, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising a semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; and said passivation film formed over said CMOS circuit.
›47.↳ 46A device according to claim 46, wherein said interlayer insulating film comprises silicon oxide.d2
A device according to claim 46, wherein said interlayer insulating film comprises silicon oxide.
›48.↳ 46A device according to claim 46, wherein said passivation film comprises silicon nitride.d2
A device according to claim 46, wherein said passivation film comprises silicon nitride.
›49.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; an interlayer insulating film formed over said first and second thin film transistor; a metal layer connected to one of said first and second thin film transistors via said interlayer insulating film; a passivation film formed over said interlayer insulating film and said metal layer; and a pixel electrode formed on said passivation film connected to the other one of said first and second thin film transistors, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising a semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, wherein said N-channel thin film transistor has a LDD structure; and said passivation film formed over said CMOS circuit.
›50.↳ 49A device according to claim 49, wherein said interlayer insulating film comprises silicon oxide.d2
A device according to claim 49, wherein said interlayer insulating film comprises silicon oxide.
›51.↳ 49A device according to claim 49, wherein said passivation film comprises silicon nitride.d2
A device according to claim 49, wherein said passivation film comprises silicon nitride.
›52.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a capacitor forming electrode formed over said substrate; a pixel electrode formed over said first and second thin film transistors and said capacitor forming electrode, said pixel electrode connected to one of said first and second thin film transistors; and a capacitor formed between said capacitor forming electrode and a portion of said semiconductor layer, a peripheral driving circuit formed over said substrate comprising a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, and a passivation film formed over said first and second thin film transistors, said capacitor forming electrode, and said CMOS circuit.
›53.↳ 52A device according to claim 52, wherein said semiconductor layer comprises crystalline silicon.d2
A device according to claim 52, wherein said semiconductor layer comprises crystalline silicon.
›54.↳ 52A device according to claim 52, wherein said passivation film comprises silicon nitride.d2
A device according to claim 52, wherein said passivation film comprises silicon nitride.
›55.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a capacitor forming electrode formed over said substrate; a pixel electrode formed over said first and second thin film transistors and said capacitor forming electrode, said pixel electrode connected to one of said first and second thin film transistors; and a capacitor formed between said capacitor forming electrode and a portion of said pixel electrode, a peripheral driving circuit formed over said substrate comprising a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, and a passivation film formed over said first and second thin film transistors, said capacitor forming electrode, and said CMOS circuit.
›56.↳ 55A device according to claim 55, wherein said semiconductor layer comprises crystalline silicon.d2
A device according to claim 55, wherein said semiconductor layer comprises crystalline silicon.
›57.↳ 55A device according to claim 55, wherein said passivation film comprises silicon nitride.d2
A device according to claim 55, wherein said passivation film comprises silicon nitride.
›58.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a capacitor forming electrode formed over said substrate; a pixel electrode formed over said first and second thin film transistors and said capacitor forming electrode, said pixel electrode connected to one of said first and second thin film transistors; a first capacitor formed between said capacitor forming electrode and a portion of said semiconductor layer, and a second capacitor formed between said capacitor forming electrode and a portion of said pixel electrode, a peripheral driving circuit formed over said substrate comprising a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, and a passivation film formed over said first and second thin film transistors, said capacitor forming electrode, and said CMOS circuit.
›59.↳ 58A device according to claim 58, wherein said semiconductor layer comprises crystalline silicon.d2
A device according to claim 58, wherein said semiconductor layer comprises crystalline silicon.
›60.↳ 58A device according to claim 58, wherein said passivation film comprises silicon nitride.d2
A device according to claim 58, wherein said passivation film comprises silicon nitride.
›61.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a passivation film formed over said first and second thin film transistors, said passivation film having at least one contact hole; a pixel electrode connected to one of said first and second thin film transistors, said pixel electrode being directly in contact with a portion of said semiconductor layer via said contact hole in said passivation film; and a capacitor forming electrode formed between said semiconductor layer and pixel electrode, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; and said passivation film formed over said CMOS circuit.
›62.↳ 61A device according to claim 61, wherein said passivation film comprises silicon nitride.d2
A device according to claim 61, wherein said passivation film comprises silicon nitride.
›63.↳ 61A device according to claim 61, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog…d2
A device according to claim 61, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog buffer.
›64.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; an interlayer insulating film formed over said first and second thin film transistors, said interlayer insulating film has at least one first contact hole; a passivation film formed over said interlayer insulating film; a second contact hole formed in said passivation film wherein said second contact hole is overlapped with said first contact hole and has a smaller diameter than said first contact hole; and a pixel electrode connected to said semiconductor layer via said second contact hole in said passivation film, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; and said passivation film formed over said CMOS circuit.
›65.↳ 64A device according to claim 64, wherein said interlayer insulating film comprises silicon oxide.d2+1
A device according to claim 64, wherein said interlayer insulating film comprises silicon oxide.
›66.↳ 65A device according to claim 65, wherein said passivation film comprises silicon nitride.d3
A device according to claim 65, wherein said passivation film comprises silicon nitride.
›67.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a passivation film formed over said first and second thin film transistors, said passivation film having at least one contact hole; a pixel electrode connected to one of said first and second thin film transistors, said pixel electrode being directly in contact with a portion of said semiconductor layer via said contact hole in said passivation film; and a capacitor forming electrode formed between said semiconductor layer and pixel electrode, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, wherein said N-channel thin film transistor has a LDD structure; and said passivation film formed over said CMOS circuit.
›68.↳ 67A device according to claim 67, wherein said passivation film comprises silicon nitride.d2
A device according to claim 67, wherein said passivation film comprises silicon nitride.
›69.↳ 67A device according to claim 67, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog…d2
A device according to claim 67, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog buffer.
›70.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; an interlayer insulating film formed over said first and second thin film transistors, said interlayer insulating film has at least one first contact hole; a passivation film formed over said interlayer insulating film; a second contact hole formed in said passivation film wherein said second contact hole is overlapped with said first contact hole and has a smaller diameter than said first contact hole; and a pixel electrode connected to a portion of said semiconductor layer via said second contact hole in said passivation film, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, wherein said N-channel thin film transistor has a LDD structure; and said passivation film formed over said CMOS circuit.
›71.↳ 70A device according to claim 70, wherein said interlayer insulating film comprises silicon oxide.d2
A device according to claim 70, wherein said interlayer insulating film comprises silicon oxide.
›72.↳ 70A device according to claim 70, wherein said passivation film comprises silicon nitride.d2
A device according to claim 70, wherein said passivation film comprises silicon nitride.
›73.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a metal layer connected to one of said first and second thin film transistors; a passivation film formed over said first and second thin film transistors and said metal layer, said passivation film having at least one contact hole; a pixel electrode connected to the other one of said first and second thin film transistors, said pixel electrode being directly in contact with a portion of said semiconductor layer via said contact hole in said passivation film; and a capacitor forming electrode formed between said semiconductor layer and pixel electrode, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; and said passivation film formed over said CMOS circuit.
›74.↳ 73A device according to claim 73, wherein said passivation film comprises silicon nitride.d2
A device according to claim 73, wherein said passivation film comprises silicon nitride.
›75.↳ 73A device according to claim 73, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog…d2
A device according to claim 73, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog buffer.
›76.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; an interlayer insulating film formed over said first and second thin film transistors, said interlayer insulating film has at least one first contact hole; a metal layer connected to one of said first and second thin film transistors via said interlayer insulating film; a passivation film formed over said interlayer insulating film and said metal layer; a second contact hole formed in said passivation film wherein said second contact hole is overlapped with said first contact hole and has a smaller diameter than said first contact hole; and a pixel electrode connected to said semiconductor layer via said second contact hole in said passivation film, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; and said passivation film formed over said CMOS circuit.
›77.↳ 76A device according to claim 76, wherein said interlayer insulating film comprises silicon oxide.d2
A device according to claim 76, wherein said interlayer insulating film comprises silicon oxide.
›78.↳ 76A device according to claim 76, wherein said passivation film comprises silicon nitride.d2
A device according to claim 76, wherein said passivation film comprises silicon nitride.
›79.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; and a pixel electrode connected to said semiconductor layer, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a gate line connected to said gate electrode in said CMOS circuit; wirings formed over said CMOS circuit and said gate line; and a contact portion between said gate line and one of said wirings formed over said substrate.
›80.↳ 79A device according to claim 79, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog…d2
A device according to claim 79, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog buffer.
›81.↳ 79A device according to claim 79, wherein said source and drain regions in said P-channel thin film transistor in said peripheral circuit include boron …d2
A device according to claim 79, wherein said source and drain regions in said P-channel thin film transistor in said peripheral circuit include boron and phosphorus.
›82.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; and a pixel electrode connected to one of said first and second thin film transistors, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, wherein said N-channel thin film transistor has a LDD structure; a gate line connected to said gate electrode in said CMOS circuit; an interlayer insulating film formed over said CMOS circuit and said gate line; wirings formed over said interlayer insulating film; and a contact portion between said gate line and one of said wirings formed over said substrate via said interlayer insulating film.
›83.↳ 82A device according to claim 82, wherein said interlayer insulating film comprises silicon oxide.d2
A device according to claim 82, wherein said interlayer insulating film comprises silicon oxide.
›84.↳ 82A device according to claim 82, wherein said source and drain regions in said P-channel thin film transistor in said peripheral circuit include boron …d2
A device according to claim 82, wherein said source and drain regions in said P-channel thin film transistor in said peripheral circuit include boron and phosphorus.
›85.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; an interlayer insulating film formed over said first and second thin film transistors; a passivation film formed over said interlayer insulating film; and a pixel electrode connected to one of said first and second thin film transistors via said passivation film, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a gate line connected to said gate electrode in said CMOS circuit; said interlayer insulating film formed over said CMOS circuit and said gate line; wirings formed over said interlayer insulating film; a contact portion formed over said substrate between said gate line and one of said wirings via said interlayer insulating film; and said passivation film formed over said CMOS circuit and said contact portion.
›86.↳ 85A device according to claim 85, wherein said interlayer insulating film comprises silicon oxide.d2
A device according to claim 85, wherein said interlayer insulating film comprises silicon oxide.
›87.↳ 85A device according to claim 85, wherein said passivation film comprises silicon nitride.d2
A device according to claim 85, wherein said passivation film comprises silicon nitride.
›88.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a pixel electrode connected to said semiconductor layer; and a capacitor forming electrode formed over said substrate and interposed between said a portion of said semiconductor layer and a portion of said pixel electrode, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a gate line connected to said gate electrode in said CMOS circuit; wirings formed over said CMOS circuit and said gate line; and a contact portion between said gate line and one of said wirings formed over said substrate.
›89.↳ 88A device according to claim 88, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog…d2
A device according to claim 88, wherein said peripheral circuit comprises at least a shift register, an analog memory, an analog switch, and an analog buffer.
›90.↳ 88A device according to claim 88, wherein said source and drain regions in said P-channel thin film transistor in said peripheral circuit include boron …d2
A device according to claim 88, wherein said source and drain regions in said P-channel thin film transistor in said peripheral circuit include boron and phosphorus.
›91.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a pixel electrode connected to one of said first and second thin film transistors; and a capacitor forming electrode formed over said substrate and interposed between said a portion of said semiconductor layer and a portion of said pixel electrode, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween, wherein said N-channel thin film transistor has a LDD structure; a gate line connected to said gate electrode in said CMOS circuit; an interlayer insulating film formed over said CMOS circuit and said gate line; wirings formed over said interlayer insulating film; and a contact portion between said gate line and one of said wirings formed over said substrate via said interlayer insulating film.
›92.↳ 91A device according to claim 91, wherein said interlayer insulating film comprises silicon oxide.d2
A device according to claim 91, wherein said interlayer insulating film comprises silicon oxide.
›93.↳ 91A device according to claim 91, wherein said source and drain regions in said P-channel thin film transistor in said peripheral circuit include boron …d2
A device according to claim 91, wherein said source and drain regions in said P-channel thin film transistor in said peripheral circuit include boron and phosphorus.
›94.independentAn active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix …+2
An active matrix device comprising: a substrate having an insulating surface; an active matrix circuit formed over said substrate, said active matrix circuit comprising: a semiconductor layer formed over said substrate; at least first and second thin film transistors formed with said semiconductor layer, each of said first and second thin film transistors comprising at least a channel forming region and source and drain regions in said semiconductor layer and at least a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; an interlayer insulating film formed over said first and second thin film transistors; a passivation film formed over said interlayer insulating film; a pixel electrode connected to one of said first and second thin film transistors via said passivation film; and a capacitor forming electrode formed over said substrate and overlapping with said a portion of said semiconductor layer and a portion of said pixel electrode, a peripheral driving circuit formed over said substrate comprising: a CMOS circuit including an N-channel thin film transistor and a P-channel thin film transistor, each of said N-channel thin film transistor and said P-channel thin film transistor comprising said semiconductor layer having a channel forming region and source and drain regions, and a gate electrode adjacent to said channel forming region with a gate insulating film interposed therebetween; a gate line connected to said gate electrode in said CMOS circuit; said interlayer insulating film formed over said CMOS circuit and said gate line; wirings formed over said interlayer insulating film; a contact portion between said gate line and one of said wirings formed over said substrate via said interlayer insulating film; and said passivation film formed over said CMOS circuit and said contact portion.
›95.↳ 94A device according to claim 94, wherein said interlayer insulating film comprises silicon oxide.d2
A device according to claim 94, wherein said interlayer insulating film comprises silicon oxide.
›96.↳ 94A device according to claim 94, wherein said passivation film comprises silicon nitride.d2
A device according to claim 94, wherein said passivation film comprises silicon nitride.