Method and device for sensing a surface temperature of an insulated gate semiconductor device

The present application is related to copending U.S. patent application Ser. No. 08/205,227, Attorney's Docket No. SC08556P, entitled "INSULATED GATE SEMICONDUCTOR DEVICE HAVING MASK MISALIGNMENT COMPENSATION AND METHOD OF FABRICATION" filed Mar. 3, 1994, by Robert B. Davies and assigned to the same assignee, Motorola, Inc.

The present application is further related to copending U.S. patent application Ser. No. 08/205,236, Attorney's Docket No. SC08538C, entitled "METHOD AND DEVICE FOR MONITORING CURRENT FLOWING IN AN INSULATED GATE SEMICONDUCTOR DEVICE" filed Mar. 3, 1994, by Robert B. Davies and assigned to the same assignee, Motorola, Inc.

The present invention relates, in general, to sensing the temperature of an integrated device, and more particularly, to a method and structure for sensing the surface temperature of an insulated gate semiconductor device.

Semiconductor device manufacturers and users share a common concern for the amount of heat dissipated by a semiconductor device. Uncontrolled temperature increases at a semiconductor device P-N junction, i.e., high heat dissipation, may result in the device failing. One technique for measuring the temperature of a P-N junction exploits the relationship between current flowing through a forward biased P-N junction and the applied voltage across the P-N junction. More particularly, the current flowing through a forward biased P-N junction varies in accordance with the applied voltage across the P-N junction, the junction area, and the junction temperature. Thus, the forward voltage drop across a P-N junction, at a constant current, can be calibrated and used as a measure of the junction temperature.

In one approach, a polysilicon temperature sensing diode is formed in a polysilicon layer on a gate oxide region of a metal-oxide-semiconductor (MOSFET) transistor. The temperature of the sensing diode increases in response to an increase in the substrate temperature whereas the forward voltage drop across the sensing diode decreases. A drawback to this technique is the presence of a substantial thermal impedance, resulting from the oxide, between the temperature sensing diode and the semiconductor substrate. Further, the resistance of a polysilicon diode can vary, thereby adding variability to the forward voltage drop across the sensing diode.

Accordingly, it would be advantageous to have a new and novel method and means for sensing the temperature of an insulated gate semiconductor device, wherein the temperature sensing portion is integrated in the same mono-crystalline substrate as the insulated gate semiconductor device.

FIGS. 1-4 illustrate enlarged cross-sectional views of a temperature sensing device in accordance with an embodiment of the present invention; and

FIG. 5 illustrates a circuit schematic of the temperature sensing device of FIGS. 1-4 in accordance with an embodiment of the present invention.

Generally, the present invention provides a special purpose PNP bipolar transistor whose collector-base junction is shorted by an insulated gate semiconductor device. The gate, drain, and source electrodes of the insulated gate semiconductor device are respectively common with the insulated gate power semiconductor device's gate, drain, and source electrodes whose on-state temperature is to be monitored. More particularly, the semiconductor device of the present invention is fabricated to permit the measurement of the surface temperature of an insulated gate semiconductor power device. This is accomplished by coupling the PNP transistor base and collector terminals to the drain and source terminals of an insulated gate field effect transistor, respectively, and applying a voltage between the gate terminal and the source terminal (V GS ) of the insulated gate field effect transistor. At a sufficient V GS , a channel is formed in the insulated gate field effect transistor which shorts a collector terminal of the PNP transistor with its base terminal. A current is driven into an emitter terminal of the diode connected PNP transistor and exits via the shorted base and collector terminals. Subsequently, a voltage drop across the PNP diode connected transistor is measured, and the voltage-current relationship of the PNP bipolar transistor is used to derive a surface temperature of the co-integrated insulated gate semiconductor power device.

FIG. 1 illustrates an enlarged cross-sectional view of a partially completed insulated gate integrated device 10 in accordance with an embodiment of the present invention. The insulated gate integrated device 10 comprises a substrate layer 11 having major surfaces 12 and 13. In a first embodiment, the substrate layer 11 is monocrystalline silicon of N conductivity type and having a resistivity ranging between approximately 0.001 ohm-centimeter (Ω-cm) and approximately 0.02 Ω-cm. In a second embodiment, the substrate layer 11 is monocrystalline silicon of P conductivity type and having a resistivity ranging between approximately 0.001 Ω-cm and approximately 0.02 Ω-cm. As those skilled in the art are aware, the insulated gate integrated device 10 will be an insulated gate field effect transistor (IGFET) or device when the substrate layer 11 is of N conductivity type, and an insulated gate bipolar transistor (IGBT) when the substrate layer 11 is of P conductivity type.

An epitaxial silicon layer 14 having a major surface 16 is formed on the major surface 13. Preferably, the epitaxial layer 14 is of N conductivity type. Methods of forming the epitaxial layer 14 are well known to those skilled in the art. Preferably, the impurity material concentration of the epitaxial layer 14 ranges between approximately 0.2 Ω-cm and approximately 400 Ω-cm. The epitaxial layer 14 serves as a drift region or a voltage supporting region for the device and will have a thickness and a resistivity to meet desired device specifications.

A conformal layer of gate oxide 17 is formed on the major surface 16. A suitable range of thicknesses for the layer of gate oxide 17 is between approximately 200 angstroms and 1,200 angstroms. By way of example, the layer of gate oxide has a thickness of 800 angstroms. An 800 angstrom thick gate oxide provides a threshold voltage ranging between approximately 2 and 4 volts for an N-channel device. A conformal layer of polysilicon (not shown) is formed on the conformal layer of gate oxide 17. A suitable range of thicknesses for the layer of polysilicon is between approximately 3,000 angstroms and approximately 7,000 angstroms. Methods of forming gate oxide layers and polysilicon layers are well known to those skilled in the art.

Using well known techniques, the layer of polysilicon is patterned to form polysilicon gate structures 19A, 19B, and 19C, which are also referred to as polysilicon gates or simply gates. More particularly, holes 18 are anisotropically etched in the layer of polysilicon to form the polysilicon gate structures 19A, 19B, and 19C. The holes or windows 18 expose portions of the gate oxide layer 17. The exposed portions of the gate oxide 17 serve as a pre-implant oxide 20 to protect the epitaxial layer 14 during subsequent implant steps.

As illustrated in FIG. 1, a thin oxide layer 15 of approximately two hundred angstroms thickness is formed on the polysilicon gates 19A, 19B, and 19C to protect them during subsequent processing steps. It shall be understood that during the formation of the thin oxide layer 15, a slight increase in the thickness of the exposed portions of the gate oxide 17 occurs, and that the formation of the thin oxide layer is optional. The thin layer of oxide 15 may be thermally grown or conformally deposited. To simplify the description of the present invention, the thin oxide layer 15 on the exposed portions of the gate oxide 17 and the exposed portions of the gate oxide 17 are collectively referred to as the pre-implant oxide 20.

An impurity material of P conductivity type is implanted through the pre-implant oxide 20, wherein the polysilicon gates 19A, 19B, and 19C serve as masks. After the implant, an anneal is performed thereby diffusing the impurity material into the epitaxial layer 14. The impurity material forms dopant wells 21 and 31 having sidewalls 22 and 32, respectively. The dopant wells 21 and 31 are also referred to as body regions. Preferably, the dopant wells 21 and 31 extend approximately 1.0 to approximately 2.5 microns into the epitaxial layer 14 from the major surface 16. It is further preferred that the impurity material of P conductivity type be boron having a surface concentration ranging from approximately 3×10 16 atoms per cubic centimeter (atoms/cm 3 ) to approximately 3×10 17 atoms/cm 3 . It shall be understood that the same reference numerals are used in the figures to denote the same elements.

Now referring to FIG. 2, the polysilicon gates 19A, 19B, and 19C and the pre-implant oxide 20 are coated or covered with a layer of photoresist 25. Openings 26 are formed in the layer of photoresist 25 to expose a portion of the pre-implant oxide 20 adjacent each side of polysilicon gates 19A, 19B, and 19C. The patterned layer of photoresist 25 serves as an implant mask. Accordingly, an impurity material of N conductivity type is implanted through the openings 26 and into the portions of the body region 21 below the exposed portions of the pre-implant oxide 20. The patterned layer of photoresist 25 is removed and an anneal is performed. The anneal repairs the silicon lattice structure in the body region 21 and diffuses the implanted impurity material into the body region 21, i.e., the anneal activates the implanted impurity ions.

The impurity material and the subsequent activation of the impurity material forms dopant or source regions 23 having sidewalls 24. Preferably, the source regions 23 extend approximately 0.15 to approximately 0.5 microns into the dopant region 21, from the major surface 16. It is further preferred that the impurity material of N conductivity type be arsenic having a surface concentration ranging from approximately 3×10 20 atoms/cm 3 to approximately 3×10 21 atoms/cm 3 . Methods of coating, patterning, and removing layers of photoresist are well known to those skilled in the art.

Now referring to FIG. 3, a layer of dielectric material (not shown) is conformally deposited over the polysilicon gates 19A, 19B, and 19C and the pre-implant oxide 20. Subsequently, sidewall spacers 27 are formed adjacent each sidewall of the polysilicon gates 19A, 19B, and 19C by anisotropically etching the layer of dielectric material. Techniques for anisotropically etching layers of dielectric material are well known to those skilled in the art.

The anisotropic etching of the conformal layer of dielectric material uncovers the portion of the pre-implant oxide 20 between the sidewall spacers 27. An impurity material of P conductivity type (i.e., the same conductivity type used, to form the body regions 21 and 31) is implanted through the uncovered portions of the pre-implant oxide 20 into the dopant wells 21 and 31. The base regions 28 and 38 are formed in the base wells 21 and 31, respectively, by activating the implanted impurity material. Further, the base regions 28 and 38 are formed underneath the source regions 23, by activating the implanted impurity material. The base regions 28 and 38 are also referred to as low resistance regions.

The sidewall spacers 27 serve as an implant mask to the ion implantation, and results in the formation of trough regions 29 within the base region 28. It shall be understood that the impurity material is implanted with sufficient energy so that only an insignificant portion of the implanted impurity material remains in the source regions 23. In other words, the implanted impurity material is implanted with sufficient energy so that the resistivity and conductivity type of the source regions 23 remain substantially unchanged.

An oxide layer 36 is conformally deposited on the polysilicon gates 19A, 19B, and 19C, oxide spacers 27, and the pre-implant oxide 20. A source/emitter opening 37 is formed in the oxide layer 36 and the pre-implant oxide 20 to expose a portion of the source region 23 and the adjacent base region 28. An emitter opening 45 is formed in the oxide layer 36 and the pre-implant oxide 20 to expose a portion of the base region 38. By way of example, the oxide layer 36 and the pre-implant 20 are anisotropically etched to form the openings 37 and 45. The oxide layer 36 may be partially wet etched resulting in a sloped sidewall as shown in FIG. 3.

Now referring to FIG. 4, a source/emitter electrode 51 is formed in the source/emitter opening 37. An emitter electrode is formed in the emitter opening 45. More particularly, the source/emitter electrode 51 electrically couples the source regions 23 and the base region 28. By way of example, the source/emitter electrode 51 is coupled to a Kelvin pad (not shown). In addition, an emitter electrode 52 is formed in the emitter opening 45.

FIG. 5 illustrates a circuit schematic of the special purpose combined PNP bipolar transistor/insulated gate transistor temperature sensing device described with reference to FIGS. 1-4. The special purpose combined PNP bipolar transistor/insulated gate transistor temperature sensing device 10 comprises an insulated gate field effect transistor 56 having a source conductor 57, a drain conductor 58, and a body conductor 59. In accordance with FIGS. 1-4, the polysilicon gate 19A is illustrated in FIG. 5 as the gate conductor 61.

The drain conductor 58 is connected to a base conductor 62 of a PNP bipolar transistor 63. The source conductor 57 is connected to body conductor 59 and to the collector conductor 64. In addition, the PNP bipolar transistor 63 has an emitter conductor 66.

In operation, a positive charge is applied to the gate conductor 61 rendering insulated gate transistor 61 operative. The current path between the source conductor 57 and the drain conductor 58, i.e., between the source region 23 and the epitaxial layer 14, shorts the base conductor 62 with the collector conductor 64, thereby configuring the PNP bipolar transistor 63 to be a diode connected PNP bipolar transistor.

A current indicated by the arrow 67 is forced into the emitter electrode 66. The current 67 flows through diode connected PNP bipolar transistor 63, with base current flowing through insulated gate field effect transistor 56, and exits transistor 56 via the source conductor 57.

The voltage drop across the forward conducting diode connected PNP bipolar transistor is measured and in conjunction with the current flowing through the diode connected PNP bipolar transistor is used to derive the surface temperature of the insulated gate semiconductor device 10.

By now it should be appreciated that an improved method and means for sensing the surface temperature of insulated gate semiconductor devices has been provided. The insulated gate field effect transistor is turned on by applying an appropriate gate-source voltage V GS . In other words, a channel region is created that converts the PNP bipolar transistor into a diode connected PNP transistor. The forward voltage drop (V F ) across the base-emitter junction is measured. Using the diode equation in conjunction with the values of V F and the current flowing through the diode connected PNP bipolar transistor, the surface temperature of the PNP bipolar transistor is determined. One advantage of the method of the present invention is that the surface temperature is derived using monocrystalline silicon which has less variability in resistance than does polysilicon. Accordingly, the forward voltage drop, V F , in the monocrystalline silicon has a greater uniformity than that of polysilicon. Another advantage is that the PNP bipolar transistor of the present invention has a current gain. Further, the diode of the present invention has less leakage current than polysilicon diodes.

While specific embodiments of the present invention have been shown and described, further modifications and improvements will occur to those skilled in the art. It is understood that the invention is not limited to the particular forms shown and it is intended for the appended claims to cover all modifications which do not depart from the spirit and scope of this invention. For example, the diode connected bipolar transistor is a PNP when the insulated gate semiconductor power device is an N-channel device. Correspondingly, when the insulated gate semiconductor power device is a P-channel device, the diode connected bipolar transistor is an NPN.