Dual-rail processors with error checking on I/O reads

A dual processor data processing system with interprocessor error checking comprising: a first central processing unit executing a series of instructions; a second central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said first central processing unit; a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit; a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit; error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses prior to delivery of said data to said first and second central processing units, said error checking means including comparison means for indicating an error when said data on said first and second data busses are unequal; and error isolation means, responsive to an error detected from said error checking means, for analyzing the cause of error while maintaining system synchronization.

A fault tolerant computing system comprising: a first processing system including a first central processing unit executing a series of instructions, a second central processing unit executing said series of instructions in the same order, independently of, and in synchronism with said first central processing unit, a first data bus coupled to said first central processing unit for receiving data to be input to said first central processing unit, a second data bus coupled to said second central processing unit for receiving data to be input to said second central processing unit, and first error checking means, coupled to said first and second data busses, for checking data transmitted over said first and second data busses and for detecting errors on I/O reads prior to delivery of said data to said first and second central processing units, said first error checking means including first comparison means for indicating an error when said data on said first and second data busses are unequal; a second processing system operating substantially synchronously with said first processing system, said second processing system including a third central processing unit executing said series of instructions, a fourth central processing unit executing said series of instructions in the same order as, independently of, and in synchronism with said third central processing unit, a third data bus coupled to said third central processing unit for receiving data to be input to said third central processing unit, a fourth data bus coupled to said fourth central processing unit for receiving data to be input to said fourth central processing unit, and second error checking means, coupled to said third and fourth data busses and for checking data transmitted over said third and fourth data busses for detecting errors on I/O reads prior to delivery of said data to said third and fourth processing systems, said second error checking system means including second comparison means for indicating an error when said data on said third and fourth data busses are unequal; and cross-link communication means coupled between said first and second processing systems for providing bidirectional synchronous communication between said first and second processing systems.