A transistor that is to be provided has such a structure that a source electrode layer and a drain electrode layer between which a channel formation region is sandwiched has regions projecting in a channel length direction at lower end portions, and an insulating layer is provided, in addition to a gate insulating layer, between the source and drain electrode layers and a gate electrode layer. In the transistor, the width of the source and drain electrode layers is smaller than that of an oxide semiconductor layer in the channel width direction, so that an area where the gate electrode layer overlaps with the source and drain electrode layers can be made small. Further, the source and drain electrode layers have regions projecting in the channel length direction at lower end portions.

Claims

22 · 3 independent · depth 3

22 granted claims

›1.independentA semiconductor device comprising: a first insulating layer; an oxide semiconductor layer over the first insulating layer; a first electrode layer ove…+6

›2.↳ 1The semiconductor device according to claim 1 , wherein the first electrode layer has a first thickness, and wherein an edge of the first electrode la…d2

›3.↳ 1The semiconductor device according to claim 1 , wherein a width of the opening of the second insulating layer in a channel length direction is larger …d2

›4.↳ 1The semiconductor device according to claim 1 , wherein a width of the opening of the second insulating layer in a channel width direction is smaller …d2

›5.↳ 1The semiconductor device according to claim 1 , wherein the second insulating layer is one selected from the group consisting of a silicon oxide film,…d2

›6.↳ 1The semiconductor device according to claim 1 , further comprising a third electrode layer under the oxide semiconductor layer with a fourth insulatin…d2+1

›8.independentA semiconductor device comprising: a first insulating layer; an oxide semiconductor layer over the first insulating layer; a first electrode layer ove…+6

›9.↳ 8The semiconductor device according to claim 8 , wherein the first electrode layer has a first thickness, and wherein an edge of the first electrode la…d2

›10.↳ 8The semiconductor device according to claim 8 , wherein a width of the opening of the second insulating layer in a channel length direction is larger …d2

›11.↳ 8The semiconductor device according to claim 8 , wherein a width of the opening of the second insulating layer in a channel width direction is smaller …d2

›12.↳ 8The semiconductor device according to claim 8 , wherein the second insulating layer is one selected from the group consisting of a silicon oxide film,…d2

›13.↳ 8The semiconductor device according to claim 8 , further comprising a third electrode layer under the oxide semiconductor layer with a fourth insulatin…d2+1

›15.independentA semiconductor device comprising: a first insulating layer; an oxide semiconductor layer over the first insulating layer; a first electrode layer ove…+7

›16.↳ 15The semiconductor device according to claim 15 , wherein the first electrode layer has a first thickness, and wherein an edge of the first electrode l…d2

›17.↳ 15The semiconductor device according to claim 15 , wherein a width of the opening of the second insulating layer in a channel length direction is larger…d2

›18.↳ 15The semiconductor device according to claim 15 , wherein a width of the opening of the second insulating layer in a channel width direction is smaller…d2

›19.↳ 15The semiconductor device according to claim 15 , wherein the second insulating layer is one selected from the group consisting of a silicon oxide film…d2

›20.↳ 15The semiconductor device according to claim 15 , further comprising a third electrode layer under the oxide semiconductor layer with a fourth insulati…d2+1

›22.↳ 15The semiconductor device according to claim 15 , further comprising a fifth insulating layer over the gate electrode layer, the fifth insulating layer…d2

Classifications

4 codes

IPC · International Patent Classification

Section H — Electricity

H01L29/786
H01L29/49
H01L29/12
H01L29/51

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2.2 y

811 days filing → grant

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non-final + final

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1 RCE

Examiner

Theresa T Doan

art unit 2814 · TC 2800

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Type	Document	Date
related publication	US 20170323974 A1	9 Nov 2017

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