Replica bit-line control circuit

This application claims the priority benefit of China application serial no. 201610585441.1, filed on Jul. 21, 2016. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.

The present invention is related to a control circuit, in particular to a replica bit-line control circuit.

Presently, SARM power consumption is mainly reduced by introducing replica bit-line control circuit 100 to SRAM to produce sensitivity amplifier enabling signals SAE and wordline control signals WL. The schematic block diagram is as shown in FIG. 1 . A replica bit-line control circuit is proposed by Amrutur B S, Horowitz M. in A replica technique for wordline and sense control in low-power SRAM's [J]. IEEE Journal of Solid-State Circuits, 1998, 33(8): 1208, which is as shown in FIG. 2 . When sense amplifier enabling signals are valid, wordline control signal WL of the replica bit-line control circuit is to be cut off through time delay by the inverter S 9 and NOR gate D 1 , which may further result in unnecessary voltage loss; furthermore, a feedback oscillation is to be produced when chip selection signal BS is set at high electrical level for a prolonged time, which may continuously charge and discharge the capacitor of replica wordline signal RWL and replica bit-line RBL to the extent of incurring unnecessary power consumption; the feedback oscillation waveform is as shown in FIG. 3 .

The technical issue to be settled by the present invention is to provide a replica bit-line control circuit that can significantly reduce SRAM power consumption.

Technical solution used by the present invention to settled aforesaid technical issues is stated as follows: A replica bit-line control circuit, comprising a replica unit, the 1 st inverter, the 2 nd inverter, the 3 rd inverter, the 4 th inverter, the 5 th inverter, the 6 th inverter, the 7 th ) inverter, the 8 th inverter and the 9 th inverter, the 1 st NAND gate, the 2 nd NAND gate, the 3 rd NAND gate, the 1 st NOR gate, the 2 nd NOR gate and the 1 st PMOS tube; the 1 st NAND gate, the 2 nd NAND gate, the 3 rd NAND gate and the 1 st NOR gate are provided with the 1 st input terminal, the 2 nd input terminal and an output terminal respectively; the 2 nd NOR gate is provided with the 1 st input terminal, the 2 nd input terminal, a set terminal and an output terminal; the said replica unit comprises a drive unit and numerous load units; the said drive unit is provided with an input/output terminal, a complementary input/output terminal and a control terminal; the said load unit is provided with an input/output terminal and a complementary input/output terminal; input/output terminal of the said drive unit is connected to input/output terminal of numerous load units, and the connecting line is the replica bit-line of the said replica unit; complementary input/output terminal of the said drive unit is connected to complementary input/output terminal of numerous load units; the 1 st input terminal of the 1 st NAND gate is the 1 st input terminal of the said replica bit-line control circuit, used to receive global wordline control signals; the 1 st input terminal of the 2 nd NAND gate is connected to the input terminal of the 3 rd NAND gate, and the connecting terminal is the 2 nd input terminal of the said replica bit-line control circuit, used to receive chip selection signals; the 2 nd input terminal of the 2 nd NAND gate is connected to the input terminal of the 9 th inverter, and the connecting terminal is the 3 rd input terminal of the said replica bit-line control circuit, used to receive writing control signals; output terminal of the 2 nd NAND gate is connected to the 1 st input terminal of the 2 nd NOR gate; output terminal of the 9 th inverter is connected to the 2 nd input terminal of the 3 rd NAND gate; output terminal of the 3 rd NAND gate and input terminal of the 8 th inverter are connected to the grid of the PMOS tube; output terminal of the 8 th inverter is connected to the 1 st input terminal of the 1 st NOR gate; output terminal of the 1 st NOR gate and the 2 nd input terminal of the 2 nd NOR gate are connected to the control terminal of the said drive unit; set terminal of the 2 nd NOR gate, drain of the 1 st PMOS tube and input terminal of the 1 st inverter are connected to the replica bit-line of the said replica unit; source of the 1 st PMOS tube is connected to the power supply; output terminal of the 2 nd NOR gate is connected to the input terminal of the 6 th inverter; output terminal of the 6 th inverter is connected to the 2 nd input terminal of the 1 st NAND gate; output terminal of the 1 st NAND gate is connected to the input terminal of the 7 th inverter; output terminal of the 7 th inverter is the 1 st output terminal of the said replica bit-line, which is used to output wordline control signals; output terminal of the 1 st inverter and input terminal of the 2 nd inverter are connected to the 2 nd input terminal of the 1 st NOR gate; output terminal of the 2 nd inverter is connected to the input terminal of the 3 rd inverter; output terminal of the 3 rd inverter is connected to the input terminal of the 4 th inverter; output terminal of the 4 th inverter is connected to the input terminal of the 5 th inverter; output terminal of the 5 th inverter is the 2 nd output terminal of the said replica bit-line control circuit, used to output sense amplifier enabling signals; the 2 nd NOR gate comprises the 2 nd PMOS tube, the 3 rd PMOS tube, the 4 th PMOS tube, the 1 st NMOS tube, the 2 nd NMOS tube and the 3 rd NMOS tube; source of the 2 nd PMOS tube and the 4 th PMOS tube is connected to the power supply respectively; drain of the 2 nd PMOS tube is connected to the source of the 3 rd PMOS tube; grid of the 2 nd PMOS tube is connected to the grid of the 2 nd NMOS tube, and the connecting terminal is the 1 st input terminal of the 2 nd NOR gate; grid of the 3 rd PMOS tube is connected to the grid of the 1 st NMOS tube, and the connecting terminal is the 2 nd input terminal of the 2 nd NOR gate; drain of the 3 rd PMOS tube, the 1 st NMOS tube and the 4 th PMOS tube is connected to the drain of the 2 nd NMOS tube, and the connecting terminal is the output terminal of the 2 nd NOR gate; source of the 1 st NMOS tube and drain of the 3 rd NMOS tube are connected to the source of the 2 nd NMOS tube; grid of the 3 rd NMOS tube is connected to the grid of the 4 th PMOS tube, and the connecting terminal is the set terminal of the 2 nd NOR gate; source of the 3 rd NMOS tube is grounded.

The said load unit comprises the 5 th PMOS tube, the 6 th PMOS tube; the 4 th NMOS tube, the 5 th NMOS tube, the 6 th NMOS tube and the 7 th NMOS tube; source of the 5 th PMOS tube, drain of the 5 th PMSO tube, drain of the 4 th NMOS tube, drain of the 6 th NMOS tube, source of the 6 th PMOS tube; grid of the 6 th PMOS tube and grid of the 5 th NMOS tube are connected to power supply respectively; grid of the 5 th PMOS tube, grid of the 4 th NMOS tube, drain of the 6 th PMOS tube and drain of the 5 th NMOS tube are connected to the drain of the 7 th NMOS tube; source of the 4 th NMOS tube, source of the 5 th NMOS tube, grid of the 6 th NMOS tube and grid of the 7 th NMOS tube are grounded respectively; source of the 6 th NMOS tube is the output terminal of the said load unit; source of the 7 th NMOS tube is the complementary input/output terminal of the said load unit. Structure of the circuit is similar to that of the memory unit in the memory array, which can effectively guard against impact from such factors as threshold voltage, power voltage and ambient temperature; furthermore, as source of the 5 th PMOS tube, drain of the 4 th NMOS tube and drain of the 6 th NMOS tube are connected to the power supply, it can effectively accommodate the slowest discharge of replica bit-line under the impact of leakage current.

The said drive unit comprises the 7 th PMOS tube, the 8 th PMOS tube, the 8 th NMOS tube, the 9 th NMOS tube, the 10 th NMOS tube and the 11 th NMOS tube; source of the 7 th PMOS tube, grid of the 7 th PMOS tube, grid of the 8 th NMOS tube, drain of the 8 th PMOS tube, source of the 8 th PMOS tube, drain of the 9 th NMOS tube and drain of the 11 th NMOS tube are connected to the power supply respectively; drain of the 7 th PMOS tube, drain of the 8 th NMOS tube, drain of the 10 th NMOS tube and grid of the 8 th PMOS tube are connected to the grid of the 9 th NMOS tube; source of the 8 th NMOS tube and source of the 9 th NMOS tube are grounded respectively; grid of the 10 th NMOS tube is connected to the grid of the 11 th NMOS tube, and the connecting terminal is the control terminal of the said drive unit; source of the 10 th NMOS tube is the input/output terminal of the said drive unit; source of the 11 th NMOS tube is the complementary input/output terminal of the said drive unit. Structure of the circuit is similar to that of the memory unit in the memory array, which can effectively guard against impact from such factors as threshold voltage, power voltage and ambient temperature; furthermore, as drain of the 7 th PMOS tube, drain of the 8 th NMOS tube and drain of the 10 th NMOS tube are grounded, it can simulate discharge of the bit-line in the memory array to the ground.

As compared with prior art, the present invention has the following advantages: When sense amplifier enabling signals are valid, it can ensure timely cutoff of wordline control signals through balancing time delay for on/off of wordline control signals to minimize switching power consumption as incurred by unnecessary discharging by the memory array pairs. Moreover, it makes use of the 2 nd NAND gate, the 3 rd NAND gate and the 9 th inverter to decompose chip selection signals to generate clock reading control signals in substitution of replica wordline signal control for charging of replica bit-line; it can effectively inhibit feedback oscillation incurred by replica bit-line and replica wordline signals to obtain accurate and stable wordline control signals for the purpose of reducing SRAM power consumption; as indicated comparison between the present invention and replica bit-line control circuit as applied to fully customized 2 Mb SRAM circuit based on the technique of SMIC 65 nm CMOS, the present invention can save the switching power consumption of memory array by 53.7% under the power voltage of 1.2V.

FIG. 1 is the structural block diagram for SRAM of existing replica bit-line control circuit;

FIG. 2 is the structural diagram for existing replica bit-line control circuit;

FIG. 3 is the feedback oscillation diagram for existing replica bit-line control circuit;

FIG. 4 is the structural diagram for the present invention;

FIG. 5 is the circuit diagram for the 2 nd NOR gate of the present invention;

FIG. 6 is the circuit diagram for the load unit of the present invention;

FIG. 7 is the circuit diagram for the drive unit of the present invention;

FIG. 8 is the structural block diagram for SRAM of the present invention;

FIG. 9 is the signal timing diagram for the present invention

The present invention is further described as follows in combination with drawings and embodiments:

Embodiment: As shown in FIG. 4 , a replica bit-line control circuit, comprising a replica unit 10 , a 1 st inverter S 1 , a 2 nd inverter S 2 , a 3 rd inverter S 3 , a 4 th inverter S 4 , a 5 th inverter S 5 , a 6 th inverter S 6 , a 7 th inverter S 7 , a 8 th inverter S 8 and a 9 th inverter S 9 , a 1 st NAND gate B 1 , a 2 nd NAND gate B 2 , a 3 rd NAND gate B 3 , a NOR gate D 1 , a 2 nd NOR gate D 2 and a PMOS tube P 1 . The 1 st NAND gate B 1 , the 2 nd NAND gate B 2 , the 3 rd NAND gate B 3 and the 1 st NOR gate D 1 are provided with the 1 st input terminal, the 2 nd input terminal and an output terminal respectively. The 2 nd NOR gate B 2 is provided with the 1 st input terminal, the 2 nd input terminal, a set terminal and an output terminal. The said replica unit 10 comprises a drive unit 10 - 1 and a plurality of load units 10 - 2 . The said drive unit 10 - 1 is provided with an input/output terminal, a complementary input/output terminal and a control terminal. Each of the said load units 10 - 2 is provided with an input/output terminal and a complementary input/output terminal; input/output terminal of the said drive unit 10 - 1 is connected to input/output terminal of the plurality of load units 10 - 2 , and the connecting line is the replica bit-line RBL of the said replica unit 10 ; the complementary input/output terminal of the said drive unit 10 - 1 is connected to complementary input/output terminal of the load units 10 - 2 ; the 1 st input terminal of the 1 st NAND gate B 1 is the 1 input terminal of the said replica bit-line control circuit, used to receive global wordline control signal GWL; the 1 st input terminal of the 2 nd NAND gate B 2 is connected to the 1 st input terminal of the 3 rd NAND gate B 3 , and the connecting terminal is the 2 nd input terminal of the said replica bit-line control circuit, used to receive chip selection signal BS; the 2 nd input terminal of the 2 nd NAND gate B 2 is connected to the input terminal of the 9 th inverter S 9 , and the connecting terminal is the 3 rd input terminal of the said replica bit-line control circuit, used to receive writing control signal WEN; output terminal of the 2 nd NAND gate B 2 is connected to the 1 st input terminal of the 2 nd NOR gate D 2 ; output terminal of the 9 th inverter S 9 is connected to the 2 nd input terminal of the 3 rd NAND gate B 3 ; output terminal of the 3 rd NAND gate B 3 and input terminal of the 8 th inverter S 8 are connected to the grid of the 1 st PMOS tube P 1 ; output terminal of the 8 th inverter S 8 is connected to the input terminal of the 1 st NOR gate D 1 ; output terminal of the 1 st NOR gate D 1 and the 2 nd input terminal of the 2 nd NOR gate D 2 are connected to the control to terminal of the said drive unit 10 - 1 ; set terminal of the 2 nd NOR gate D 2 , drain of the 1 st PMOS tube P 1 and input terminal of the 1 st inverter S 1 are connected to the replica bit-line of the said replica unit 10 ; source of the 1 st PMOS tube P 1 is connected to the power supply VDD; output terminal of the 2 nd NOR gate D 2 is connected to the input terminal of the 6 th inverter S 6 ; output terminal of the 6 th inverter S 6 is connected to the 2 nd input terminal of the 1 st NAND gate B 1 ; output terminal of the 1 st NAND gate B 1 is connected to the input terminal of the 7 th inverter S 7 ; output terminal of the 7 th inverter S 7 is the 1 st output terminal of the said replica bit-line, which is used to output wordline control signal WL; output terminal of the 1 st inverter S 1 and input terminal of the 2 nd inverter S 2 are connected to the 2 nd input terminal of the 1 st NOR gate D 1 ; output terminal of the 2 nd inverter S 2 is connected to the input terminal of the 3 rd inverter S 3 ; output terminal of the 3 rd inverter S 3 is connected to the input terminal of the 4 th inverter S 4 ; output terminal of the 4 th inverter S 4 is connected to the input terminal of the 5 th inverter S 5 ; output terminal of the 5 th inverter S 5 is the 2 nd output terminal of the said replica bit-line control circuit, used to output sense amplifier enabling signal SAE;

As shown in FIG. 5 , the 2 nd NOR gate D 2 comprises a 2 nd PMOS tube P 2 , a 3 rd PMOS tube P 3 , a 4 th PMOS tube P 4 , a 1 st NMOS tube N 1 , a 2 nd NMOS tube N 2 and a 3 rd NMOS tube N 3 ; source of the 2 nd PMOS tube P 2 and the 4 th PMOS tube P 4 is connected to the power supply VDD respectively; drain of the 2 nd PMOS tube P 2 is connected to the source of the 3 rd PMOS tube P 3 ; grid of the 2 nd PMOS tube P 2 is connected to the grid of the 2 nd NMOS tube N 2 , and the connecting terminal is the 1 st input terminal of the 2 nd NOR gate D 2 ; grid of the 3 rd PMOS tube P 3 is connected to the grid of the 1 st NMOS tube N 1 , and the connecting terminal is the 2 nd input terminal of the 2 nd NOR gate D 2 ; drain of the 3 rd PMOS tube P 3 , the 1 st NMOS tube N 1 and the 4 th PMOS tube P 4 is connected to the drain of the 2 nd NMOS tube N 2 , and the connecting terminal is the output terminal of the 2 nd NOR gate D 2 ; source of the NMOS tube N 1 and drain of the 3 rd NMOS tube N 3 are connected to the source of the 2 nd NMOS tube N 2 ; grid of the 3 rd NMOS tube N 3 is connected to the grid of the 4 th PMOS tube P 4 , and the connecting terminal is the set terminal of the 2 nd NOR gate D 2 ; source of the 3 rd NMOS tube N 3 is grounded VSS.

As shown in FIG. 6 , each of the load unit 10 - 2 in this embodiment comprises a 5 th PMOS tube P 5 , a 6 th PMOS tube P 6 , a 4 th NMOS tube N 4 , a 5 th NMOS tube N 5 , a 6 th NMOS tube N 6 and a 7 th NMOS tube N 7 . A source of the 5 th PMOS tube P 5 , a drain of the 5 th PMSO tube P 5 , a drain of the 4 th NMOS tube N 4 , a drain of the 6 th NMOS tube N 6 , a source of the 6 th PMOS tube P 6 , a grid of the 6 th PMOS tube P 6 and a grid of the 5 th NMOS tube N 5 are connected to power supply VDD respectively. A grid of the 5 th PMOS tube P 5 , a grid of the 4 th NMOS tube N 4 , a drain of the 6 th PMOS tube P 6 and a drain of the 5 th NMOS tube N 5 are connected to a drain of the 7 th NMOS tube N 7 . A source of the 4 th NMOS tube N 4 , a source of the 5 th NMOS tube N 5 , a grid of the 6 th NMOS tube N 6 and a grid of the 7 th NMOS tube N 7 are grounded VSS respectively. A source of the 6 th NMOS tube N 6 is the output terminal of the said load unit 10 - 2 . A source of the 7 th NMOS tube N 7 is the complementary input/output terminal of the said load unit 10 - 2 .

As shown in FIG. 7 , the drive unit 10 - 1 in this embodiment comprises a 7 th PMOS tube P 7 , a 8 th PMOS tube P 8 , a 8 th NMOS tube N 8 , a 9 th NMOS tube N 9 , a 10 th NMOS tube N 10 and a 11 th NMOS tube N 11 . Source of the 7 th PMOS tube P 7 , grid of the 7 th PMOS tube P 7 , grid of the 8 th NMOS tube N 8 , drain of the 8 th PMOS tube P 8 , source of the 8 th PMOS tube P 8 , drain of the 9 th NMOS tube N 9 and drain of the 11 th NMOS tube N 11 are connected to the power supply VDD respectively; drain of the 7 th PMOS tube P 7 , drain of the 8 th NMOS tube N 8 , drain of the 10 th NMOS tube N 10 and grid of the 8 th PMOS tube P 8 are connected to the grid of the 9 th NMOS tube N 9 ; source of the 8 th NMOS tube N 8 and source of the 9 th NMOS tube N 9 are grounded VSS respectively; grid of the 10 th NMOS tube N 10 is connected to the grid of the 11 th NMOS tube N 11 , and the connecting terminal is the control terminal of the said drive unit 10 - 1 ; source of the 10 th NMOS tube N 10 is the input/output terminal of the said drive unit 10 - 1 ; source of the 11 th NMOS tube N 11 is the complementary input/output terminal of the said drive unit 10 - 1 .

In this embodiment, the 1 st inverter S 1 , the 2 nd inverter S 2 , the inverter S 3 , the 4 th inverter S 4 , the 5 th inverter S 5 , the 6 th inverter S 6 , the 7 th inverter S 7 , the 8 th inverter S 8 , the 9 th inverter S 9 , the 1 st NAND gate B 1 , the 2 nd NAND gate B 2 , the 3 rd NAND gate B 3 and the 1 st NOR gate D 1 are well-established products of prior arts.

Wiring block diagram for the replica bit-line control circuit 1 of the present invention as applied to SRAM is as shown in FIG. 8 .

Working principle of the replica bit-line control circuit 1 of the present invention is stated as follows: writing clock control signal WCLK at the beginning of writing operation can directly control the wordline enabling signal WLEN to determine on/off of the wordline control signal of memory array 2 in together with global wordline control signal. For reading operation, signal timing for the replica bit-line control circuit 1 of the present invention is as shown in FIG. 9 ; wherein, BL and BLB represent a bit-line pair used for charging in the memory array; prior to the commencement of reading cycle, reading clock control signal RCLK is to be maintained at a low electrical level; whereas replica bit-line of the replica unit 10 RBL is to be set at a high electrical level; replica wordline signal RWL, wordline control signal WL and sense amplifier enabling signal SAE are to be set at a low electrical level; at the beginning of reading operation, reading clock control signal RCLK and replica wordline signal RWL are to be set at a high electrical level to control discharging of line capacitor of replica bit-line RBL by the replica unit 10 ; meanwhile, global wordline control signal GWL is to be set at a high electrical level; replica wordline signal RWL makes use of the 2 nd NOR gate D 2 , the 6 th inverter S 6 , the 1 st NAND gate B 1 and the 7 th inverter S 7 to generate valid wordline control signal WL to control discharging of the bit-line BL and BLB by memory unit of the memory array 2 . When replica bit-line is set at a low electrical level, sense amplifier enabling signal SAE is to be set at a high electrical level to turn on the sense amplifier 3 following time delay of the 1 st inverter S 1 ˜the 5 th inverter S 5 ; as the 2 nd NOR gate D 2 is controlled by replica bit-line RBL of the replica unit 10 , on/off of wordline control signal WL is not to be determined by replica wordline signal RWL; once replica bit-line RBL of the replica unit 10 is set at a high electrical level, it is applicable to make use of the 2 nd NOR gate, the 6 inverter S 6 , the 1 st NAND gate B 1 and the 7 th inverter S 7 to turn off wordline control signal WL, eliminate the time delay incurred by the 1 st inverter S 1 and the 1 st NOR gate D 1 , and make the opening time T pulse,WL of wordline control signal WL equal to the discharging time T rbl of replica bit-line RBL. As a result, wordline control signal WL can be turned off in time to prevent unnecessary power consumption, and significantly reduce SRAM power consumption when the sense amplifier 3 is turned on.