Array substrate and display device

The application is a U.S. National Phase Entry of International Application PCT/CN2014/081130 filed on Jun. 30, 2014, designating the United States of America and claiming priority to Chinese Patent Application No. 201310731356.8, filed on Dec. 26, 2013. The present application claims priority to and the benefit of the above-identified applications and the above-identified applications are incorporated by reference herein in their entirety.

Embodiments of the present invention relate to an array substrate and a display device with the array substrate.

A thin film transistor liquid crystal display (TFT-LCD) is a common liquid crystal display. In the TFT LCD, each gate line needs to be connected to a corresponding gate driver to drive a thin film transistor disposed in each pixel unit in a display region, so as to display an image. As one kind of gate driver technology, the Gate Driver on Array (GOA) technology is now commonly utilized in the field of TFT-LCD. In GOA, the gate driver is fabricated directly in a GOA region on an array substrate in place of externally connected driving chips.

As known by an inventor, a wiring of the gate driver in the GOA region is implemented by metal wires disposed in two layers, by using the metal wires respectively in the same layer as a gate driving element, such as a gate and source/drain of thin film transistor as connecting lines of a gate driver.

However, to avoid a short circuit caused by an intersection of the metal wires or too narrow space between the metal wires in the same layer, a space between any two metal wires in the GOA region is relatively large, thus, resulting in a relatively large width of the GOA region, which makes a limitation to a narrow-frame design. Furthermore, it is easy for the metal wires in the same layer to be intersected or have too narrow space therebetween, thus, which is likely to cause the short circuit.

Embodiments of the present invention provide an array substrate and a display device having the array substrate, which can satisfy the requirement of narrow-frame design and avoid a short circuit caused by an intersection of the metal wires or too narrow space between the metal wires in a GOA region.

In one aspect, an embodiment of the present invention provides an array substrate, a display region; a non-display region, disposed at the periphery of the display region, comprising: a gate driver region (GOA region), comprising: a first patterned metal layer, formed on a base substrate; a first insulating layer, formed on the first patterned metal layer; a second patterned metal layer, formed on the first insulating layer; a second insulating layer, covering the second patterned metal layer; and a third patterned metal layer, formed at a side of the second insulating layer away from the base substrate, wherein the third patterned metal layer comprises a plurality of metal wires insulated from each other and connected to the first patterned metal layer and the second patterned metal layer respectively by through holes and used as connecting lines between elements of the gate driver.

In another aspect, an embodiment of the present invention also provides an array substrate as mentioned above; and an opposed substrate, cell-assembled with the array substrate.

In order to clearly illustrate the technical solution of the embodiments of the invention, the drawings of the embodiments will be briefly described in the following; it is obvious that the described drawings are only related to some embodiments of the invention and thus are not limitative of the invention.

FIG. 1 is a schematic cross-sectional view of a GOA region of an array substrate according to a first embodiment of the present invention;

FIG. 2 is a schematic cross-sectional view of a GOA region of an array substrate according to a second embodiment of the present invention; and

FIG. 3 is a schematic cross-sectional view of a GOA region of an array substrate according to a third embodiment of the present invention.

FIG. 4A is a schematic cross-sectional view of a GOA region of an array substrate according to a fourth embodiment of the present invention.

FIG. 4B is a schematic cross-sectional view of a GOA region of an array substrate according to a fifth embodiment of the present invention.

FIG. 5 is a schematic cross-sectional view of a GOA region of an array substrate according to a sixth embodiment of the present invention.

FIG. 6 is a schematic cross-sectional view of a GOA region of an array substrate according to a seventh embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of a GOA region of an array substrate according to a seventh embodiment of the present invention.

In order to make objects, technical details and advantages of the embodiments of the invention apparent, the technical solutions of the embodiment will be described in a clearly and fully understandable way in connection with the drawings related to the embodiments of the invention. It is obvious that the described embodiments are just a part but not all of the embodiments of the invention. Based on the described embodiments herein, those skilled in the art can obtain other embodiment(s), without any inventive work, which should be within the scope of the invention.

A First Embodiment

The first embodiment of the present invention provides an array substrate comprising a display region and a non-display region at the periphery of the display region, the non-display region comprises a gate driver region (a GOA region). FIG. 1 is a cross-sectional view of the GOA region. As shown in FIG. 1 , the GOA region comprises: a first patterned metal layer 1 , formed on a base substrate 10 ; a first insulating layer 2 , formed on the first patterned metal layer 1 ; a second patterned metal layer 3 , formed on the first insulating layer 2 ; and a second insulating layer 4 , covering the second patterned metal layer 3 , wherein at a side of the second insulating layer 4 away from the base substrate, a third patterned metal layer 5 is formed and comprises a plurality of metal wires respectively connected to the first patterned metal layer 1 and the second patterned metal layer 3 by through holes and used as connecting lines between elements of a gate driver. Therefore, by disposing the connection lines of the gate driver in the third patterned metal layer, the space occupied by wirings in the GOA region is reduced, thus, a width of the GOA region can be reduced and the narrow-frame design can be achieved.

Exemplarily, at least one of the plurality of metal wires is used to connect the first patterned metal layer and the second patterned metal layer; or, all of the plurality of metal wires are used to connect the first patterned metal layer and the second patterned metal layer.

FIG. 1 is a schematic view showing a case in that a metal wire in the third patterned metal layer 5 connects a gate in the first patterned metal layer 1 and another source/drain in the second patterned metal layer 3 , but this is only an example and the third patterned metal layer may implement various connections in practice.

Alternatively, the plurality of metal wires further comprise a metal wire with one end connected to a metal pattern in the first patterned metal layer and the other end connected to another metal pattern in the first patterned metal layer (as shown in FIG. 4A and FIG. 7 ) and/or a metal wire with one end connected to a metal pattern in the second patterned metal layer and the other end connected to another metal pattern in the second patterned metal layer (as shown in FIG. 4B and FIG. 7 ).

Exemplarily, a driving element disposed in the GOA region is, for example, a thin film transistor, and in a condition that the thin film transistor is a bottom-gate type thin film transistor, the first patterned metal layer 1 comprises a gate, the first insulating layer 2 is a gate insulating layer, the second patterned metal layer 3 comprises a source/drain, and the second insulating layer 4 is a passivation layer. In addition, a patterned active layer 23 is disposed between the first insulating layer 2 and the second patterned metal layer 3 in the GOA region for forming a channel of the thin film transistor, as shown in FIG. 5 .

Exemplarily, the driving element disposed in the GOA region is, for example, a thin film transistor, and in a condition that the thin film transistor is a top-gate type thin film transistor, the first patterned metal layer 1 comprises a source/drain, the first insulating layer 2 is a gate insulating layer, the second patterned metal layer 3 comprises a gate, and the second insulating layer 4 is a passivation layer. In addition, a patterned active layer 23 is disposed between the first patterned metal layer 1 and the first insulating layer 2 in the GOA region, as shown in FIG. 6 .

Exemplarily, when a plurality of thin film transistors are disposed in the GOA region, as shown in FIG. 1 , at least one metal wire in the third patterned metal layer is used to connect a gate of a thin film transistor and a source/drain of another thin film transistor. Alternatively, a metal wire in the third patterned metal layer may connect a patterned metal in the first patterned metal layer and a patterned metal in the second patterned metal payer as required by a GOA circuit, those skilled in the art may make an option based on the actual requirement and FIG. 1 only shows an example and does not make any limitation to an embodiment of the present invention.

Alternatively, the plurality of metal wires are insulated from each other by an insulating layer 9 coplanar with the third patterned metal layer 5 .

In this way, in the array substrate according to an embodiment of the present invention, the third patterned metal layer is further disposed in the GOA region, and the metal wires in the third patterned metal layer may be used as connecting lines of an element in a gate driver and as some or all of signal lines of the gate driver. As a result, the locations of the signal lines and the connecting lines are transferred from the same layer as the elements to over the elements, and the first patterned metal layer and the second patterned metal layer of the gate driver can be connected by one metal wire using through holes, thus, an area of the GOA region can be greatly reduced.

A Second Embodiment

Since the third patterned metal layer 5 is connected to the first patterned metal layer 1 and the second patterned metal layer 3 respectively by the through holes, in the present embodiment, a transparent conducting layer 7 is further formed between the second insulating layer 4 and the third patterned metal layer 5 based on the structure in the first embodiment so as to avoid the third patterned metal layer 5 to be broken at positions where the through holes are disposed.

As shown in FIG. 2 , an array substrate comprises a first patterned metal layer 1 , a first insulating layer 2 , a second patterned metal layer 3 , a second insulating layer 4 , the transparent conducting layer 7 and a third patterned metal layer 5 formed in a GOA region on a base substrate 10 , wherein the third patterned metal layer 5 comprises a plurality of metal wires insulated from each other and connecting the first patterned metal layer 1 and the second patterned metal layer 3 respectively by using through holes. By disposed the transparent conducting layer 7 as an interlayer, the third patterned metal layer 5 can be avoided to be broken at positions where the through holes are disposed.

Exemplarily, the transparent conducting layer and the plurality of metal wires in the third patterned metal layer are conformal, especially, at the through holes of the second insulating layer 4 , the transparent conducting layer and the plurality of metal wires in the third patterned metal layer are conformal.

A Third Embodiment

In the present embodiment, a third insulating layer 6 is formed between the second insulating layer 4 and the transparent conducting layer 7 based on the structure according to the second embodiment so as to reduce a capacitance between the third patterned metal layer 5 and the second patterned metal layer 3 and the first patterned metal layer 1 . Herein, a through hole is formed in the third insulating layer and a thickness of the third insulating layer 6 is in a range of 1˜2 μm. Within this thickness range, the capacitance between the third patterned metal layer and a thin film transistor in the GOA region can be effectively reduced, and the feasibility of the process can be insured (the thickness of the third patterned metal layer being very large will lead to the great processing difficulty) and the utilization effect of the array substrate can be guaranteed.

As shown in FIG. 3 , an array substrate comprises a first patterned metal layer 1 , a first insulating layer 2 , a second patterned metal layer 3 , a second insulating layer 4 , the third insulating layer 6 , a transparent conducting layer 7 and a third patterned metal layer 5 formed in a GOA region on a base substrate 10 , wherein the third patterned metal layer 5 comprises a plurality of metal wires insulated from each other and connecting the first patterned metal layer 1 and the second patterned metal layer 3 respectively by using through holes. By adding the third insulating layer 6 , the parasitic capacitance between the third patterned metal layer 5 and the first patterned metal layer 1 and between the third patterned metal layer 5 and the second patterned metal layer 3 can be reduced, interference to signals can be reduced and the display quality can be improved.

A Fourth Embodiment

The present embodiment is different from the third embodiment only in that the array substrate does not comprise a transparent conducting layer 7 , and a third insulating layer 6 with through holes formed therein is directly formed between the second insulating layer 4 and the third patterned metal layer 5 .

A Fifth Embodiment

The fifth embodiment of the present invention provides a display device comprising: an array substrate according to any one of the first to the fourth embodiments described above; and an opposed substrate, cell-assembled with the array substrate. The display device may be a liquid crystal television set, a smartphone or a tablet computer, etc.

Exemplarily, in a technical solution according to embodiments of the present invention, material of the metal wires in the third patterned metal layer may be commonly used material, for example, a metal for a gate or a source/drain, those skilled in the art may make a selection according to the actual situation, which is not limited in embodiments of the present invention.

With the array substrate according to an embodiment of the present invention, a third patterned metal layer is further disposed in a GOA region, and metal wires therein may be used as connecting lines of elements in a gate driver and as some or all of signal lines in the gate driver. As a result, the locations of the signal lines and the connecting lines are transferred from the same layer as the elements to over the elements, and the first patterned metal layer and the second patterned metal layer of the gate driver can be connected by one metal wire using through holes, thus, an area of the GOA region can be greatly reduced. Furthermore, by adding a thick resin, that is, the third insulating layer between the third patterned metal layer and the first patterned metal layer and between the third patterned metal layer and the second patterned metal layer, the coupling capacitance can be reduced and the display quality can be further improved.

The embodiment of the invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to those skilled in the art are intended to be included within the scope of the following claims.

The present application claims priority of China patent application No. 201310731356.8 filed on Dec. 26, 2013, which is incorporated herein by reference in its entirety.