Method of forming interconnects for three dimensional integrated circuit

The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from repeated reductions in minimum feature size, which allows more components to be integrated into a given area. As the demand for even smaller electronic devices has grown recently, there has grown a need for smaller and more creative packaging techniques of semiconductor dies.

As semiconductor technologies evolve, three dimensional integrated circuits have emerged as an effective alternative to further reduce the physical size of a semiconductor chip. In a three dimensional integrated circuit, active circuits such as logic, memory, processor circuits and the like are fabricated on different wafers and each wafer die is stacked on top of a packaging component using pick-and-place techniques. Much higher density can be achieved by employing three dimensional integrated circuits. In sum, three dimensional integrated circuits can achieve smaller form factors, cost-effectiveness, increased performance and lower power consumption.

A three dimensional integrated circuit may comprise an integrated circuit die, an interposer and a package substrate. More particularly, the integrated circuit die is attached to a first side of the interposer through a plurality of solder bumps. Solder bumps are used to provide electrical connection between the integrated circuit die and the interposer. A second side of the interposer is attached to the package substrate by a plurality of interconnect bumps. Interconnect bumps such as solder balls may provide electrical connection between the interposer and the package substrate, which in turn makes electrical connection to a printed circuit board through a plurality of package leads.

In order to reduce the potential solder failure between the integrated circuit die and the package substrate caused by thermal stresses, the interposer is employed to provide a matching coefficient of thermal expansion to the integrated circuit die. The interposer also provides adaptation between smaller contact pads with reduced pitch on an integrated circuit die and larger contact pads with increased pitch on a package substrate. In addition, the interposer may further comprise a variety of circuit elements. These circuit elements may be active, passive, or a combination of active and passive elements.

Three dimensional integrated circuits have some advantages. One advantageous feature of packaging multiple semiconductor dies vertically is that three dimensional package techniques may reduce fabrication costs. Another advantageous feature of three dimensional semiconductor devices is that parasitic losses are reduced by employing various interconnect bumps.

For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a cross sectional view of a three dimensional integrated circuit in accordance with an embodiment;

FIG. 2 illustrates a cross sectional view of placing an interposer on a first carrier in accordance with an embodiment;

FIG. 3 illustrates a cross sectional view of the semiconductor device shown in FIG. 2 after the dielectric layer has been removed in accordance with an embodiment;

FIG. 4 illustrates a cross sectional view of the semiconductor device shown in FIG. 3 after a plurality of through vias are formed in the interposer in accordance with an embodiment;

FIG. 5 illustrates a cross sectional view of the semiconductor device shown in FIG. 4 after a second carrier is mounted on top of the interposer in accordance with an embodiment;

FIG. 6 illustrates a process of removing the first carrier from the semiconductor device shown in FIG. 5 ;

FIG. 7 illustrates a cross sectional view of forming a plurality of openings in a photoresist layer in accordance with an embodiment;

FIG. 8 illustrates a cross sectional view of the semiconductor device shown in FIG. 7 after the exposed portions of the copper foil layer have been removed; and

FIG. 9 illustrates a cross sectional view of the semiconductor device shown in FIG. 8 after the photoresist layer has been removed in accordance with an embodiment.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the embodiments of the disclosure, and do not limit the scope of the disclosure.

The present disclosure will be described with respect to embodiments in a specific context, a three dimensional integrated circuit. The embodiments of the disclosure may also be applied, however, to a variety of semiconductor devices. Hereinafter, various embodiments will be explained in detail with reference to the accompanying drawings.

FIG. 1 illustrates a cross sectional view of a three dimensional integrated circuit in accordance with an embodiment. A three dimensional integrated circuit 100 may comprise an integrated circuit die 102 stacked on a package component 106 . As shown in FIG. 1 , the integrated circuit die 102 is attached to a first side of the package component 106 through a plurality of interconnect components including metal pillar bumps 122 , micro bumps 120 and redistribution layer 124 . In addition, there may be an encapsulation layer 104 formed on top of the packaging component 106 . In particular, the integrated circuit 102 and the interconnect components (e.g., micro bumps 120 and redistribution layer 124 ) are embedded in the encapsulation layer 104 .

In accordance with an embodiment, the packaging component 106 may be an interposer. For simplicity, throughout the description, the packaging component 106 may be alternatively referred to as an interposer 106 . The interposer 106 may be made of silicon, glass and/or the like. As shown in FIG. 1 , the interposer 106 may comprise a plurality of vias 116 embedded in the interposer 106 . The interposer 106 may further comprise a first side redistribution layer 124 formed on top of the first side of the interposer 106 . After the integrated circuit die 102 is bonded on the interposer 106 , the active circuits of the integrated circuit die 102 are coupled to the vias of the interposer 106 through a conductive channel formed by the redistribution layer 124 , micro bumps 120 and the metal pillar bumps 122 .

A second side of the interposer 106 may be attached to a package substrate (not shown) by a plurality of interconnect bumps 110 . In accordance with an embodiment, these interconnect bumps 110 may be solder balls. As shown in FIG. 1 , the redistribution layer 124 is connected to its corresponding through via 116 . Furthermore, the through via 116 is connected to its corresponding interconnect bump 110 through a redistribution layer 114 and an under bump metallization structure 112 . As such, the metal pillar bump 122 , solder ball 120 , the redistribution layer 124 , the through via 116 , the redistribution layer 114 , the under bump metallization structure 112 and the interconnect bump 110 may form a conductive path between the active circuits of the integrated circuit die 102 and the package substrate (not shown), which in turn makes electrical connection to a printed circuit board or the like through a plurality of package leads.

FIGS. 2-9 are cross sectional views of intermediate stages in the making of redistribution layers and through vias in accordance with an embodiment. FIG. 2 illustrates a cross sectional view of placing an interposer on a first carrier in accordance with an embodiment. The first carrier 202 may be formed of a wide variety of materials comprising glass, silicon, ceramics and/or the like.

As shown in FIG. 2 , a metal layer 206 is temporarily attached to the first carrier 202 . In accordance with an embodiment, the metal layer 206 may be a copper foil layer. Alternatively, the metal layer 206 may be other suitable conductive materials such as copper alloys, aluminum, tungsten, silver and combinations thereof. Throughout the description, for simplicity, the metal layer 206 is alternatively referred to as a copper foil layer 206 . The copper foil layer 206 is mounted on the carrier 202 . In particular, the copper foil layer 206 may be glued on top of the first carrier 202 by employing a first adhesive layer (not shown). In accordance with an embodiment, the first adhesive layer may be formed of epoxy and/or the like.

A dielectric layer 204 is formed on top of the copper foil layer 206 . The dielectric layer 204 may be formed of either photoresist materials or non-photoresist materials. In accordance with an embodiment, the dielectric layer 204 may be formed of photoresist materials such as polybenzoxazole (PBO), SU-8 photo-sensitive epoxy, film type polymer materials and/or the like.

The interposer 106 may be formed of silicon, glass and the like. There may be a plurality of through holes 208 embedded in the interposer 106 . In accordance with an embodiment, the interposer 106 is of a thickness in a range from about 50 um to about 800 um. The interposer 106 is mounted on the first carrier 202 . In particular, the interposer 106 may be glued on top of the copper coil layer 206 by employing the dielectric layer 204 .

FIG. 3 illustrates a cross sectional view of the semiconductor device shown in FIG. 2 after the dielectric layer has been removed in accordance with an embodiment. The exposed portions of the dielectric layer shown in FIG. 2 may be removed by using suitable techniques such as chemical developing, laser ablation, dry etching and/or the like. The removal techniques are well known and hence are not discussed in further detail herein to avoid repetition.

FIG. 4 illustrates a cross sectional view of the semiconductor device shown in FIG. 3 after a plurality of through vias are formed in the interposer 106 in accordance with an embodiment. As shown in FIG. 4 , an electrochemical plating process may be performed on the interposer 106 so that a conductive material fills the through holes (e.g., through hole 208 shown in FIG. 2 ) to form a plurality of through vias 116 . The conductive material may be copper, but can be any suitable conductive materials, such as copper alloys, aluminum, tungsten, silver and combinations thereof. In a subsequent electrochemical plating process of forming through vias, the copper foil layer 206 may function as an electrode to facilitate the electrochemical deposition process.

In a conventional through silicon via (TSV) fabrication process, the fabrication steps may include depositing a seed layer, plating conductive materials on the seed layer, applying a chemical mechanical polishing (CMP) process and performing a thinning process to expose through vias. The method described above with respect to FIG. 4 does not require a seed layer. Instead, a bottom-up electrochemical plating process is performed on the copper foil layer (e.g., copper foil layer 206 ). One advantageous feature of having a bottom-up electrochemical plating process is that the bottom-up electrochemical plating process can prevent some manufacture defects such as voids trapped in through vias, which may deteriorate the overall reliability of a three dimensional integrated circuit. In addition, applying the bottom-up electrochemical plating process on the copper foil layer without requiring a seed layer may reduce operating costs and improve efficiency. Furthermore, the bottom-up electrochemical plating process can provide additional benefits such as deposition processes insensitive to sidewall surface roughness and less limitations on the aspect ratio of through vias.

FIG. 5 illustrates a cross sectional view of the semiconductor device shown in FIG. 4 after a second carrier 502 is mounted on top of the interposer 106 in accordance with an embodiment. The second carrier 502 is similar to the first carrier 202 , and hence is not discussed in further detail. There may be a second adhesive layer (not shown) between the second carrier 502 and the interposer 106 . In accordance with an embodiment, the second adhesive layer is formed of epoxy and/or the like.

FIG. 6 illustrates a process of removing the first carrier from the semiconductor device shown in FIG. 5 . In accordance with an embodiment, the first carrier 202 can be detached from the interposer 106 . A variety of detaching processes may be employed to separate the interposer 106 from the first carrier 202 . The variety of detaching processes may comprise a chemical solvent, a UV exposure and the like.

FIG. 7 illustrates a cross sectional view of forming a plurality of openings in a photoresist layer in accordance with an embodiment. A photoresist layer 702 is formed on top of the copper foil layer 206 over the interposer 106 . The photoresist material may comprise SU-8 photo-sensitive epoxy, film type polymer materials and/or the like. In consideration of electrical and thermal needs, selective areas of the photoresist layer 702 are exposed to light. As a result, a variety of openings (e.g., opening 704 ) are formed. The formation of the openings such as opening 704 in the photoresist layer 702 involves lithography operations, which are well known, and hence are not discussed in further detail herein.

FIG. 8 illustrates a cross sectional view of the semiconductor device shown in FIG. 7 after the exposed portions of the copper foil layer have been removed. In accordance with an embodiment, a suitable etching process such as wet-etching, dry-etching or the like may be applied to the exposed portions of the copper foil layer 206 shown in FIG. 7 . As a result, the exposed portions of the copper foil layer 206 have been removed. The detailed operations of either the dry etching process or the wet etching process are well known, and hence are not discussed herein to avoid repetition.

FIG. 9 illustrates a cross sectional view of the semiconductor device shown in FIG. 8 after the photoresist layer has been removed in accordance with an embodiment. The remaining photoresist layer 702 shown in FIG. 8 may be removed by using suitable photoresist stripping techniques such as chemical solvent cleaning, plasma ashing, dry stripping and/or the like. The photoresist stripping techniques are well known and hence are not discussed in further detail herein to avoid repetition.

It should be recognized that while FIG. 9 illustrates the interposer 106 with a single redistribution layer (e.g., redistribution layer 114 ), the interposer 106 could accommodate any number of redistribution layers. The number of redistribution layers illustrated herein is limited solely for the purpose of clearly illustrating the inventive aspects of the various embodiments. The present disclosure is not limited to any specific number of redistribution layers.

One advantageous feature of forming a redistribution layer based upon a copper foil layer is that the redistribution layer can be obtained by an etching process without depositing a seed layer and applying an electrochemical plating process. Such a copper foil based redistribution layer helps to reduce operating costs and improve efficiency.

Although embodiments of the present disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims.

Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the present disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.