Accurate hysteretic comparator and method

This invention relates generally to the field of electrical circuits. More specifically, the present invention is directed to the design of an analog signal comparator.

An analog signal comparator is a common functional building block for numerous analog electrical circuits. A hysteretic signal comparator has a hysteresis loop around its reference signal and is, for example, commonly employed in a feedback electrical control circuit to avoid, in the absence of such a hysteresis loop, undesirable excessive oscillations of a controlled signal around its target value.

FIG. A 1 illustrates a prior art U.S. Pat. No. 6,229,350 entitled “Accurate, fast, and user programmable hysteretic comparator” by Ricon-Mora et al, hereinafter referred to as U.S. Pat. No. 6,229,350. FIG. A 1 illustrates the prior art hysteretic comparator 1 and FIG. A 2 illustrates its signal input/output (I/O) characteristics 2 . FIG. A 2 applies to any hysteretic comparator. The key I/O signals of the prior art hysteretic comparator 1 are a pair of input signals VIN A and VIN B and a 2-level output signal VOT. To those skilled in the art, in reference to input signal VIN B the VOT vs. VIN A characteristics of FIG. A 2 exhibit a level transition around VIN A =VIN B with a hysteresis window of V hys =2*ΔV.

The prior art hysteretic comparator 1 has the following major functional blocks coupled to one another:

A Differential_Input_Stage for differentially converting the input signal pair VIN A and VIN B into intermediate current signals. A Summing_Node and an Output_Gain_Stage for converting and amplifying the intermediate current signals into the final 2-level output signal VOT. A Steerable_offset_current_generator for generating and injecting, through its Current_steering_switch, an offset current into the Differential_Input_Stage thus producing the hysteresis window of V hys in the VOT vs. VIN A characteristics. A Signal_inverter is included to convert VOT into differential control signals required internally by the Steerable_offset_current_generator. Notice that V hys is further made user programmable through a “V control ” signal applied to the Steerable_offset_current_generator. Current_mirrors, rooted in a current source “I BIAS ”, to supply a number of bias currents required by the Differential_Input_Stage and the Steerable_offset_current_generator.

As is known to those skilled in the art, the hysteresis window V hys of the prior art hysteretic comparator 1 is governed by the following equations:

In the above equations, G m(input) refers to the transconductance of the differential transistor pair Q 2 and Q 5 within the Differential_Input_Stage. G m(offset) refers to the transconductance of the differential transistors Q 16 , Q 17 , Q 26 and Q 27 within the Steerable_offset_current_generator. G m refers to the transconductance of a generic transistor. V GS and V th refer respectively to the gate-source voltage and threshold voltage of a generic transistor. Knp is a transistor device parameter sensitive to its numerous fabrication processing tolerances. C ox is the gate oxide capacitance per area.

To be an accurate hysteretic comparator, V hys should be fabricated with tight tolerance and should exhibit low sensitivity to environmental variations such as temperature. From the above equations (1)-(4) it can be seen that the fractional variation of V hys tracks that of G m(input) and G m(offset) . Furthermore, any mismatch of G m amongst the transistor pairs (for example, between Q 2 and Q 5 ) would cause an additional variation of V hys . While this phenomenon applies to both bipolar and MOS transistors, the degree of V hys variation becomes especially serious with CMOS transistors. Unlike bipolar transistors, the G m of a CMOS transistor is small and G m of CMOS transistors do not match as well. In the prior art, for good matching and large transconductance the size of each of the differential CMOS transistors Q 16 , Q 17 , Q 26 , Q 27 must become similar in size as each of the input CMOS transistors Q 2 , Q 5 . That means a large integrated circuit (IC) die area would be consumed to implement a simple comparator function, an expensive and unfeasible proposition. Therefore, there exists a need to create a simple hysteretic comparator with an accurate hysteresis window V hys without consuming a large IC die area.

A hysteretic comparator (HYSCP) is proposed for comparing two input signal voltages VIN A , VIN B and producing a 2-level output signal VOT reflecting the relative magnitude between VIN A and VIN B with an accurate hysteresis window V hys . The HYSCP includes:

A differential input stage with current output (DICO) having a number of differentially connected input transistors with transistor transconductance Gm tnx for converting VIN A and VIN B , with an input stage transconductance Gm in , into corresponding intermediate signal currents IIN A and IIN B . A steerable offset current generator (SOCG) having a built-in offset current source IOS, two output offset currents IOS A , IOS B and a current steering switch driven by a steering control signal and coupled to the IOS for, depending upon the logic state of the steering control signal, steering the IOS through either IOS A or IOS B . A current-to-voltage summing converter (IVSC) connected to the IIN A , IOS A , IIN B and IOS B for respectively summing the currents (IIN A , IOS A ) and the currents (IIN B , IOS B ) and converting the summed currents into the 2-level output signal VOT plus the steering control signal having its logic states corresponding to the VOT levels thus causing V hys =IOS/Gm in . The input transistors are connected so as to create negative feedback loops within the DICO that largely negates the transistor transconductance Gm tnx from the input stage transconductance Gm in . The DICO further includes a feedback resistance R NF connected to the input transistors and, additionally, the R NF is sized relative to the input transistors such that Gm in becomes dominated by and essentially equal to the feedback conductance G NF =1/R NF independent of the Gm tnx , whose large variation over transistor fabrication process and device operating environment would otherwise cause a corresponding inaccuracy of the V hys .

In a more specific embodiment, the number of differentially connected input transistors further includes:

A differentially connected pair of input switching transistor TNX SA and input switching transistor TNX SB with their (transistor transconductance, output impedance) respectively equal to (Gm SA , R SA ) and (Gm SB , R SB ). A differential pair of input load transistor TNX LA and input load transistor TNX LB , respectively coupled to TNX SA and TNX SB in a staggered configuration to create negative feedback loops, with their (transistor transconductance, output impedance) respectively equal to (Gm LA , R LA ) and (Gm LB , R LB ). Correspondingly, the R NF is sized to meet the following criterion:

1 R NF >> Gm SA Gm LA ⁢ R SA + Gm SB Gm LB ⁢ R SB

The pair of input switching transistor TNX SA and input switching transistor TNX SB , and the pair of input load transistor TNX LA and input load transistor TNX LB , are designed such that their transistor transconductances largely cancel out. This can be easily accomplished by making transistors of the same size and parameters.

For converting VIN A and VIN B into the intermediate signal current IIN A , the DICO further includes a number of IIN A -referencing current sources plus a current mirror connected to TNX SA and TNX LA . For converting VIN A and VIN B into the intermediate signal current IIN B , the DICO further includes a number of IIN B -referencing current sources plus a current mirror connected to TNX SB and TNX LB .

In a more specific embodiment, the current steering switch has a pair of differentially connected steering transistors in turn connected to the IOS for respectively supplying IOSA and IOSB. The steering control signal has a pair of differential steering signals respectively coupled to a control terminal of the steering transistors.

In a more specific embodiment, the IVSC includes:

A summing transistor TNX SUMA connected to the currents (IIN A , IOS A ) for summing them up and converting the summation into an interim differential output signal Vio A . A summing transistor TNX SUMB connected to the currents (IIN B , IOS B ) for summing them up and converting the summation into an interim differential output signal Vio B . An output gain stage (OGS) coupled to the interim differential output signals (Vio A , Vio B ) for amplifying them into the VOT and generating the steering control signal.

These aspects of the present invention and their numerous embodiments are further made apparent, in the remainder of the present description, to those of ordinary skill in the art.

In order to more fully describe numerous embodiments of the present invention, reference is made to the accompanying drawings. However, these drawings are not to be considered limitations in the scope of the invention, but are merely illustrative.

FIG. A 1 illustrates a prior art hysteretic comparator under U.S. Pat. No. 6,229,350;

FIG. A 2 illustrates signal input/output characteristics of a hysteretic comparator;

FIG. 1A illustrates the present invention hysteretic comparator;

FIG. 1B illustrates another embodiment of the present invention hysteretic comparator; and

FIG. 1C illustrates another embodiment of the present invention hysteretic comparator.

The description above and below plus the drawings contained herein merely focus on one or more currently preferred embodiments of the present invention and also describe some exemplary optional features and/or alternative embodiments. The description and drawings are presented for the purpose of illustration and, as such, are not limitations of the present invention. Thus, those of ordinary skill in the art would readily recognize variations, modifications, and alternatives. Such variations, modifications and alternatives should be understood to be also within the scope of the present invention.

FIG. 1A illustrates the present invention hysteretic comparator (HYSCP) 10 . The present invention HYSCP 10 functions to compare two input signal voltages VIN A , VIN B and produce a 2-level output signal VOT reflecting the relative magnitude between VIN A and VIN B with an accurate hysteresis window V hys . The graph showing the hysteresis window V hys (=2ΔV) in FIG. A 2 also applies to this invention. The HYSCP includes:

A differential input stage with current output (DICO) 12 having a number of differentially connected input transistors with transistor transconductance Gm tnx for converting VIN A and VIN B , with an input stage transconductance Gm in , into corresponding intermediate signal currents IIN A and IIN B . A steerable offset current generator (SOCG) 14 having a built-in offset current source IOS 14 a , two output offset currents IOS A , IOS B and a current steering switch 14 b driven by a pair of steering control signals SCS A and SCS B jointly called steering control signals (SCS)) and coupled to the IOS 14 a for, depending upon the logic state of the SCS, steering the IOS 14 a through either offset current IOS A or offset current IOS B . The current steering switch 14 b has two source-coupled steering transistors 14 c and 14 d. A current-to-voltage summing converter (IVSC) 40 connected to the IIN A , IOS A , IIN B and IOS B for respectively summing the currents (IIN A , IOS A via summing transistor TNX SUMA 40 a ) and the currents (IIN B , IOS B via summing transistor TNX SUMB 40 b ) and converting the summed currents into the 2-level output signal VOT plus SCS having its logic states corresponding to the VOT levels thus causing V hys =IOS/Gm in . As a key element of the present invention, the DICO 12 further includes a feedback resistance R NF 12 m connected to the input transistors. Additionally, the feedback resistance R NF 12 m is sized relative to the input transistors such that Gm in , becomes dominated by and essentially equal to the feedback conductance G NF =1/R NF independent of the Gm tnx , whose large variation over transistor fabrication process and device operating environment would otherwise cause a corresponding inaccuracy of the V hys .

As a more detailed embodiment, the number of differentially connected input transistors further includes:

A differentially connected pair of input switching transistors TNX SA 12 a and TNX SB 12 b . The TNX SA 12 a has its (transistor transconductance, output impedance) equal to (Gm SA , R SA ) while the TNX SB 12 b has its (transistor transconductance, output impedance) equal to (Gm SB , R SB ). A differential pair of input load transistors TNX LA 12 c and TNX LB 12 d respectively coupled to TNX SA 12 a and TNX SB 12 b in a staggered configuration for an increased gain and to create negative feedback loops. The TNX LA 12 c has its (transistor transconductance, output impedance) equal to (Gm LA , R LA ) while the TNX LB 12 d has its (transistor transconductance, output impedance) equal to (Gm LB , R LB ). The gate of 12 c may be coupled to the drain of 12 a , and the drain of 12 c may be coupled to the source of 12 a . Likewise, the gate of 12 d may be coupled to the drain of 12 b , and the drain of 12 d may be coupled to the source of 12 b.

With the introduction of the R NF 12 m , the governing equations for the present invention hysteresis window V hys become:

V hys = 2 ⁢ ⁢ Δ ⁢ ⁢ V = IOS Gm in ( 5 ) Gm in = Gm SA Gm LA ⁢ R SA + 1 R NF + Gm SB Gm LB ⁢ R SB ( 6 )

The SOCG 14 may be implemented in different ways, but should include the output offset currents IOS A and IOS B . Equation (5) may be written more generally as:

Hence, according to the present invention, when the R NF 12 m is sized to meet the following criterion:

1 R NF >> Gm SA Gm LA ⁢ R SA + Gm SB Gm LB ⁢ R SB ( 7 )

The governing equations for the present invention hysteresis window V hys become essentially independent of the various transistor device parameters. That is:

V hys ≈IOS*R NF   (8)

In addition, the transistors are designed such that the transconductances Gm SA and Gm LA are approximately equal (the same with transconductances Gm SB and Gm LB ), and largely cancel out such that equation (6) becomes:

Gm in ≈ 1 R SA + 1 R NF + 1 R SB

thus eliminating the transconductances of the transistors from the equation. The criterion of Equation (7) then becomes:

1 R NF >> 1 R SA + 1 R SB

which is simple to accomplish since the impedances of the transistors are large, for example around 1MΩ. So the expression of Gm in simplifies to:

As the value of an IC resistor is, when compared to the (transistor transconductance, output impedance) of the above input switching transistors and input load transistors, substantially less sensitive to the fabrication process variation and device operating environment, the present invention has achieved a simple hysteretic comparator with an accurate hysteresis window V hys without consuming a large IC die area. For example, the poly resistors made from an IC process can be controlled within an approximate 5% accuracy or even better while the corresponding transistor transconductance can vary over a 20% range.

For converting VIN A and VIN B into the intermediate signal current IIN A , the DICO 12 further includes a number of IIN A -referencing current sources 12 e , 12 f plus a current mirror (formed by transistor M 6 and TNX LA 12 c ) connected to TNX SA 12 a and TNX LA 12 c . Current source 12 e is connected to the gate of TNX LA 12 c and should be smaller than current source 12 f (e.g., by a half) which is connected to the source of TNX SA 12 a . For converting VIN A and VIN B into the intermediate signal current IIN B , the DICO 12 further includes a number of IIN B -referencing current sources 12 g , 12 h plus a current mirror (formed by transistor M 3 and TNX LB 12 d ) connected to TNX SB 12 b and TNX LB 12 d . Current source 12 g is connected to the gate of TNX LB and should be smaller than current source 12 h which is connected to the source of TNX SB 12 b.

As another more detailed alternative embodiment, the summing transistor TNX SUMA 40 a would sum up the currents (IIN A , IOS A ) and convert the summation into an interim differential output signal Vio A . Similarly, the summing transistor TNX SUMB 40 b would sum up the currents (IIN B , IOS B ) and convert the summation into an interim differential output signal Vio B . Subsequently, an output gain stage (OGS) 42 , coupled to the interim differential output signals (Vio A , Vio B ), would amplify them into the 2-level output signal VOT while simultaneously generate the steering control signals (SCS). By way of example, the OGS 42 may generate the SCS using two inverters in series.

In the HYSCP 10 of FIG. 1A , the transistors 12 a , 12 b are p-channel transistors, and the transistors 12 c , 12 d are n-channel transistors. However, as an alternative embodiment of the present invention the transistor type may be reversed and this is illustrated in a HYSCP 70 of FIG. 1B which is similar to HYSCP 10 except that the transistor channel types are reversed, as are the directions of the currents and voltages. In the HYSCP 70 , the transistors 72 a , 72 b are n-channel transistors respectively replacing transistors 12 a , 12 b . Likewise, the transistors 72 c , 72 d are p-channel transistors respectively replacing transistors 12 c , 12 d . The other transistors 100 a , 100 b , 74 c , 74 d , M 63 , M 66 also change channel type and respectively replace transistors 40 a , 40 b , 14 c , 14 d , M 3 , M 6 , while the current sources 72 e , 72 f , 72 g , 72 h , 74 a take the place of and switch directions as compared to current sources 12 e , 12 f , 12 g , 12 h , 14 a of the HYSCP 10 of FIG. 1A . Note that although the side of the DICO 12 closest to the current sources 72 f and 72 g is at a higher voltage than the side of the DICO 12 closest to the IVSC 40 , it is still shown as ground for the purposes of this description.

As additional alternative embodiments of the present invention, the negative feedback loop may be formed in various ways. FIG. 1C illustrates another HYSCP 90 in which all the circuit elements are the same as those of the HYSCP 10 of FIG. 1A except for portions of the DICO 12 of FIG. 1A now relabeled as 92 . In the DICO 92 , the transistors 12 a , 12 b , 12 c , 12 d , are not staggered with 12 c placed instead in series with 12 a and 12 d placed in series with 12 b . The transistors 12 c and 12 d each has gate to drain shorts to form current mirrors with transistors M 6 and M 3 respectively. The current sources 12 e and 12 g of FIG. 1A are eliminated from FIG. 1C . Instead, the DICO 92 includes operational amplifiers OpAmp A 12 i and OpAmp B 12 j , whose outputs are connected to the gate of transistors 12 a , 12 b , respectively. One input of op amps 12 i , 12 j is connected to VIN A , VIN B , respectively, and the other input is connected to the source of transistors 12 a , 12 b , respectively. The op amps 12 i , 12 j provide a negative feedback loop to the input transistors 12 a , 12 b , which minimizes the contributions of the transistor transconductance Gm tnx to the input stage transconductance Gm in hence the hysteretic window V hys , as explained below.

The input stage transconductance Gm in is:

In the above Gm 12a and Gm 12b are the transconductance of transistors 12 a and 12 b respectively, and [op amp loop gain] 12i and [op amp loop gain] 12j are the op amp loop gain of op amps 12 i and 12 j respectively. The op amp loop gain is defined as:

op amp loop gain=1+( A*B )

Wherein A is the open loop gain of the amplifier, and B is the feedback factor. In the configuration as shown, the feedback factor equals one, so Equation (9) becomes:

As the open loop gain of an op amp is by definition a very large value, the input transistor transconductances Gm 12a and Gm 12b are essentially negated from contributing to the input stage transconductance Gm in and the equation simplifies to:

Gm in ≈ 1 R NF

the same conclusion as the HYSCP 10 of FIG. 1 .

Throughout the description and drawings, numerous exemplary embodiments were given with reference to specific configurations. It will be appreciated by those of ordinary skill in the art that the present invention can be embodied in numerous other specific forms and those of ordinary skill in the art would be able to practice such other embodiments without undue experimentation. For example, while the present invention is illustrated using MOS transistors the same inventive concept can be alternatively embodied in bipolar transistor circuit as well. The scope of the present invention, for the purpose of the present patent document, is hence not limited merely to the specific exemplary embodiments of the foregoing description, but rather is indicated by the following claims. Any and all modifications that come within the meaning and range of equivalents within the claims are intended to be considered as being embraced within the spirit and scope of the present invention.