Inverter device

The present invention relates to an inverter device, and relates more particularly to an inverter device having a circuit for preventing improper operation and voltage breakdown of a high withstand voltage IC used for drive control of a bridge circuit including switching elements driving a load.

As taught in Japanese Patent Laid-open Publication No. 10-42575, conventional inverter devices have a clamp diode connected between a high voltage reference terminal and low voltage reference terminal of a high withstand voltage IC used for drive controlling switching elements for handling negative surges resulting from line inductance and current variation per unit time, di/dt, when switching a switching element driving a load.

Basic technological premise of this invention, and problems therewith

FIG. 8 is a schematic circuit diagram showing connection of the above-noted clamp diode. It should be noted that FIG. 8 shows only the peripheral circuits of one exemplary high withstand voltage IC, for example, the high withstand voltage IC for switching control of switching elements driving a load connected to the external connection terminal U to which the load is connected.

Clamp diode 102 is connected between high voltage side reference terminal Vs and low voltage side reference terminal VSS of high withstand voltage IC 101 ; high withstand voltage IC 101 controls operation of switching element 104 connected between external power supply terminal P to which a positive supply voltage is applied, and external terminal U to which a load is connected. The high withstand voltage IC controlling operation of switching element 105 connected between external terminal U and external power supply terminal N to which a negative supply voltage is applied is omitted in this figure.

Voltage V (Vs−VSS) is held by clamp diode 102 to the forward voltage of clamp diode 102 only when a negative potential surge causes voltage V (Vs−VSS) between high voltage side reference terminal Vs and low voltage side reference terminal VSS to become a negative voltage.

However, if the impedance of the load connected to external terminal U is low, heavy current flows when the load is driven, and the negative potential surge reaches several tens of volts, a negative potential greater than or equal to the withstand voltage of the high withstand voltage IC 101 . The voltage is applied because of the delay due to the normal recovery time and the V-I characteristic of clamp diode 102 when a heavy current of several hundred amperes, for example, flows. It is therefore not possible for clamp diode 102 alone to sufficiently suppress the negative voltage applied to the high withstand voltage IC 101 , resulting in improper operation, and, in some cases, breakdown of high withstand voltage IC 101 .

The present invention resolves the above described problem, and an object of this invention is to provide an inverter apparatus preventing breakdown and improper operation of a high withstand voltage IC that controls the switching operation of switching elements for driving a load.

An inverter apparatus according to the present invention includes an inverter circuit part for inverter driving a load. This inverter circuit part has at least a pair of switching elements connected in series in a forward direction between both polarity terminals of a dc supply for supplying power to a load. An inverter drive circuit part is employed for driving each switching element of the inverter circuit part and has at least one high withstand voltage IC wherein the signal level reference potential is different in the input signal and output signal. A clamping circuit part clamps the potential of the low voltage side reference terminal, to which a potential that is a reference for operation of the high withstand voltage IC in the inverter drive circuit part and is a reference for a signal on the low potential side of the high withstand voltage IC is applied, to the high voltage reference terminal to which is applied a reference potential for the high potential-side signal in the high withstand voltage IC. The inverter apparatus also includes a voltage dividing circuit part for voltage dividing a voltage between the low voltage side reference terminal of the high withstand voltage IC in the inverter drive circuit part and the negative electrode of the dc supply.

By thus providing a voltage dividing circuit part for voltage dividing a voltage between the low voltage reference terminal of the high withstand voltage IC and the negative electrode of the dc supply, a negative voltage applied between the high voltage reference terminal and the low voltage reference terminal of the high withstand voltage IC is prevented from going below the minimum rated withstand voltage of the high withstand voltage IC.

The voltage dividing circuit part can also be disposed to each high withstand voltage IC.

Preferably, the voltage dividing circuit part is an element functioning as a voltage dividing resistance connected between the low voltage side reference terminal of the high withstand voltage IC in the inverter drive circuit part and the negative electrode of the dc supply, in which case the voltage dividing circuit part is an element effecting a voltage dividing resistance, such as one resistor or one inductance.

Further preferably, the low voltage side reference terminal of the high withstand voltage IC in the inverter drive circuit part is connected by way of a diode to elements functioning as the clamping circuit part and voltage dividing resistance, and current flows from the voltage dividing resistance in the direction of the low voltage reference terminal of the high withstand voltage IC.

Yet further preferably, the bypass circuit part for bypassing the voltage dividing circuit part is disposed to each voltage dividing circuit part so that high withstand voltage IC operating current output from the low voltage reference terminal flows to the negative electrode of the dc supply.

More specifically, this bypass circuit part is a bypass diode for bypassing the voltage dividing circuit part, and the bypass circuit part comprises one bypass diode.

FIG. 1 is a schematic circuit diagram showing an example of an inverter apparatus according to a first embodiment of the present invention;

FIG. 2 is a circuit diagram showing the peripheral circuits of a high withstand voltage IC of FIG. 10;

FIG. 3 is a schematic circuit diagram showing another example of an inverter apparatus according to a first embodiment of the present invention;

FIG. 4 shows a circuit example of a high withstand voltage IC shown in FIG. 3;

FIG. 5 is a schematic circuit diagram showing an example of an inverter apparatus according to a second embodiment of the present invention;

FIG. 6 is a schematic circuit diagram showing another example of an inverter apparatus according to the second embodiment of the present invention;

FIG. 7 is a schematic circuit diagram showing another example of an inverter apparatus according to the second embodiment of the present invention;

FIG. 8 is a partial circuit diagram showing an example of a conventional inverter apparatus.

The preferred embodiments of the present invention are described below with reference to the accompanying figures.

FIG. 1 is a schematic circuit diagram showing an example of an inverter apparatus according to a first embodiment of the present invention. It should be noted that FIG. 1 shows an example of a three-phase inverter apparatus.

In FIG. 1, three-phase inverter apparatus 1 comprises a voltage inverter 2 comprising six IGBT switching elements Q 1 to Q 6 and parallel connected diodes D 1 to D 6 corresponding to switching elements Q 1 to Q 6 , and an inverter drive circuit 3 for driving the voltage inverter.

In voltage inverter 2 , collectors of switching elements Q 1 to Q 3 are each connected to external power supply terminal P for applying a positive supply voltage to voltage inverter 2 , at that time a corresponding line inductance Lc 1 to Lc 3 is formed between the collector and external power supply terminal P. Emitters of switching elements Q 4 to Q 6 are connected to the external power supply terminal N for applying a negative supply voltage to voltage inverter 2 , at that time a corresponding line inductance Le 4 to Le 6 is formed between each emitter and the external power supply terminal N.

The emitter of switching element Q 1 and the collector of switching element Q 4 are each connected to external connection terminal U for connecting a load, and line inductance Le 1 between the emitter and external connection terminal U, and line inductance Lc 4 between the collector and external connection terminal U. are respectively formed. Likewise, the emitter of switching element Q 2 and the collector of switching element Q 5 are each connected to external connection terminal V for connecting a load, and line inductance Le 2 between the emitter and external connection terminal V, and line inductance Lc 5 between the collector and external connection terminal V, are respectively formed. Likewise, the emitter of switching element Q 3 and the collector of switching element Q 6 are each connected to external connection terminal W for connecting a load, and line inductance Le 3 between the emitter and external connection terminal W, and line inductance Lc 6 between the collector and external connection terminal W, are respectively formed.

In addition, the gates of switching elements Q 1 to Q 6 are connected to inverter drive circuit 3 by way of intervening corresponding resistors R 1 to R 6 ; inverter drive circuit 3 controls switching of switching elements Q 1 to Q 6 according to an input control signal. A dc supply VDC is connected between external power supply terminal P and external power supply terminal N, and a reactor (not shown in the figures) is connected as a load to external connection terminals U, V, W.

High withstand voltage ICs 11 to 16 for driving switching elements Q 1 to Q 6 are disposed in inverter drive circuit 3 for each switching element Q 1 to Q 6 of the voltage inverter 2 , and a clamp diode D 11 to D 16 is disposed between the high voltage side reference terminal Vs and low voltage side reference terminal VSS of each high withstand voltage IC 11 to 16 so that the direction from low voltage side reference terminal VSS to high voltage side reference terminal Vs is forward. The low voltage side reference terminal VSS of each high withstand voltage IC 11 to 16 is connected by way of intervening protection circuit 21 , comprising voltage-dividing resistance R 21 and bypass diode D 21 parallel connected to voltage-dividing resistance R 21 , to external power supply terminal N and to external ground terminal GND.

Control signal input terminal IN of each high withstand voltage IC 11 to 16 is respectively connected to a corresponding external control signal input terminal Up, Vp, Wp, Un, Vn, Wn, and positive supply input terminal VCC and low voltage side reference terminal VSS functioning as the negative supply input terminal are respectively connected to the positive and negative electrodes of dc supply 22 .

It should be noted that because high withstand voltage ICs 11 to 16 all have the same circuit configuration, the internal circuitry of only high withstand voltage IC 13 is shown in FIG. 1, and the internal circuitry of high withstand voltage ICs 11 , 12 , and 14 to 16 is omitted. As a result, the operation of high withstand voltage IC 13 is described below, and further description of the operation of the other high withstand voltage ICs is omitted because their operation is the same as that of high withstand voltage IC 13 .

High withstand voltage IC 13 comprises an input buffer 25 , n-channel MOS transistor (referred to below as “NMOS transistor”) 26 , resistor R 27 , and driver circuit 28 . The input terminal of input buffer 25 is connected to control signal input terminal IN, the output terminal is connected to the gate of NMOS transistor 26 , the positive supply input terminal is connected to positive-supply input terminal VCC, and the negative supply input terminal is connected to low voltage side reference terminal VSS.

The drain of NMOS transistor 26 is connected to resistor R 27 and the input terminal of driver circuit 28 , and the source of NMOS transistor 26 is connected to low voltage side reference terminal VSS. NMOS transistor 26 and resistor R 27 form a level shifter 29 for shifting the output signal of input buffer 25 to generate a signal of a floating potential floating from the potential of the output signal. In driver circuit 28 the output terminal is connected to output terminal OUT of high withstand voltage IC 13 , the positive supply input terminal is connected to positive floating supply input terminal Vb, and the negative supply input terminal is connected to high voltage side reference terminal Vs functioning as the negative floating supply input terminal. The input buffer 25 , driver circuit 28 , and level shifter 29 thus form a level shifting circuit. In addition, a corresponding dc source 31 to 36 is connected between positive floating supply input terminal Vb and high voltage side reference terminal Vs in each high withstand voltage IC 11 to 16 .

Thus comprised, the operation of protection circuit 21 is described below with reference to FIG. 2, FIG. 2 being a circuit diagram showing the peripheral circuits to high withstand voltage IC 13 in FIG. 1 . It should be noted that the line inductances are omitted in FIG. 2. A reactor as a load is connected to external connection terminals U to W; the negative potential surge (referred to below as “negative surge”) caused between external connection terminal U and external power supply terminal N as a result of switching switching element Q 1 , for example, is voltage divided by voltage-dividing resistance R 21 and clamp diode D 13 of protection circuit 21 .

When the resistance of voltage-dividing resistance R 21 is high, operating current I 1 of high withstand voltage IC 13 flowing from low voltage side reference terminal VSS to external power supply terminal N is limited by resistance R 21 , and operating current I 1 bypass flows through bypass diode D 21 parallel connected to resistance R 21 . It will be obvious that if the resistance of voltage-dividing resistance R 21 is low enough that it has no problem-causing effect on operating current I 1 , bypass diode D 21 can be omitted.

It should be noted that a high withstand voltage IC for driving switching elements Q 1 to Q 6 is described by way of example with reference to FIG. 1 and FIG. 2, but the invention shall not be so limited and can be applied to a high withstand voltage IC used for switching element drive control. For example, the invention can be applied to a level shift circuit for driving a switching element, and a high withstand voltage IC comprising a level shift circuit functioning as an overcurrent detection circuit for detecting overcurrent flow to a switching element. FIG. 3 shows another example of an inverter apparatus according to this first embodiment in this case, and FIG. 4 shows an exemplary circuit for the high withstand voltage IC shown in FIG. 3 .

It should be noted that FIG. 3 shows an example of the high withstand voltage IC connected to switching element Q 1 of inverter apparatus 1 shown in FIG. 1 and peripheral circuitry, and other high withstand voltage ICs and peripheral circuits are omitted because they are the same. Furthermore, in FIG. 3 and FIG. 4 like parts are identified by the same reference numerals shown in FIG. 1, and further description thereof is omitted below where only the differences from FIG. 1 are described.

Differences between FIG. 3 and FIG. 1 are that the emitters of switching elements Q 1 to Q 3 are connected to corresponding external connection terminals U to W by way of intervening current detection resistors R 41 to R 43 , and the emitters of switching elements Q 4 to Q 6 are connected to external power supply terminal N by way of intervening current detection resistors R 44 to R 46 , the internal circuits of high withstand voltage ICs 11 to 16 in FIG. 1 are changed, and NOR gates N 41 to N 46 are added.

In FIG. 3, one input terminal to NOR gates N 41 to N 46 is an inverting input terminal for inverting the input signal level, and the other input terminal is a non-inverting input terminal that does not invert the input signal level. The control signal input terminals IN of high withstand voltage ICs 11 a to 16 a are connected to the output terminal of corresponding NOR gates N 41 to N 46 , and the non-inverting input terminals of NOR gates N 41 to N 46 are respectively connected to corresponding external control signal input terminals Up, Vp, Wp, Un, Vn, Wn.

The node between the emitter of each switching element Q 1 to Q 6 and the corresponding resistor R 41 to R 46 is connected to input terminal Fin of high withstand voltage ICs 11 a to 16 a , and the corresponding output terminal Fout of high withstand voltage ICs 11 a to 16 a is connected to the inverting input terminal of the corresponding NOR gate N 41 to N 46 .

The operation of high withstand voltage IC 13 a is described below using FIG. 4, and because operation of the other high withstand voltage ICs 11 a , 12 a , and 14 a to 16 a is the same as high withstand voltage IC 13 a , further description thereof is omitted below.

High withstand voltage IC 13 a comprises input buffers 25 and 41 , NMOS transistor 26 , p-channel MOS transistor (referred to below as “PMOS transistor”) 42 , resistors R 27 and R 47 , and driver circuits 28 and 44 . In input buffer 41 the input terminal is connected to input terminal Fin, the output terminal is connected to the gate of PMOS transistor 42 , the positive supply input terminal is connected to positive floating supply input terminal Vb, and the negative supply input terminal is connected to high voltage side reference terminal Vs.

The drain of PMOS transistor 42 is connected to resistor R 47 and the input terminal of driver circuit 44 , and the source of PMOS transistor 42 is connected to positive floating supply input terminal Vb. PMOS transistor 42 and resistor R 47 form level shifter 49 for down shifting the output signal from input buffer 41 and generating a signal of a potential referenced to the ground level. In driver circuit 44 the output terminal is connected to output terminal Fout of high withstand voltage IC 13 a , the positive supply input terminal is connected to positive supply input terminal VCC, and the negative supply input terminal is connected to low voltage side reference terminal VSS. The input buffer 25 , driver circuit 28 , and level shifter 29 thus form a level shift circuit for shifting the input signal level up, and input buffer 41 , driver circuit 44 , and level shifter 49 form a level shift circuit for shifting the input signal level down.

Thus comprised, high withstand voltage IC 13 a drives switching element Q 1 according to a control signal input from external control signal input terminal Up through NOR gate 43 to the corresponding control signal input terminal IN, and from the voltage obtained from resistor R 41 detects an overcurrent flowing to switching element Q 1 . If an overcurrent flows to switching element Q 1 , a high level signal is input to input terminal Fin of high withstand voltage IC 13 a , and high withstand voltage IC 13 a outputs a low level signal from output terminal Fout while this high level signal is input.

When a low level signal is input to the inverting input terminal of NOR gate N 43 , the output terminal goes high regardless of control signal input from external control signal input terminal Up, the output terminal OUT of high withstand voltage IC 13 a goes low, and switching element Q 1 switches off. It should be noted that connection of clamp diodes D 11 to D 16 and protection circuit 21 to high withstand voltage ICs 11 a to 16 a is the same as in high withstand voltage IC 11 to 16 in FIG. 1, and further description thereof is thus omitted.

An inverter apparatus according to a first embodiment of the present invention thus has a protection circuit 21 comprising bypass diode D 21 parallel connected to a voltage-dividing resistance R 21 disposed between low voltage side reference terminal VSS of the high withstand voltage IC and external power supply terminal N for applying a negative supply voltage to voltage inverter 2 . It is therefore possible by adding a simple circuit to prevent a negative voltage applied between the high voltage side reference terminal Vs and low voltage side reference terminal VSS of each high withstand voltage IC from dropping below the minimum rated withstand voltage between the terminals due to a negative surge produced when switching a switching element, and it is therefore possible to inexpensively prevent improper operation and withstand voltage breakdown of the high withstand voltage IC.

One protection circuit 21 protects against breakdown of each high withstand voltage IC due to a negative surge in the above-described first embodiment, but a protection circuit 21 can be disposed to each high withstand voltage IC, and a configuration of this type is described next as a second embodiment of the present invention.

FIG. 5 is a schematic circuit diagram showing an inverter apparatus according to a second embodiment of the present invention. It should be noted that like parts are identified by like reference numerals in FIG. 5 and FIG. 1 . Further description thereof is thus omitted here, and only the differences therebetween are described.

The differences in FIG. 5 and FIG. 1 are that in place of protection circuit 21 in FIG. 1 protection circuits 61 to 66 , each comprising a bypass diode and parallel connected voltage-dividing resistor, are disposed to high withstand voltage IC 11 to 16 , respectively. As a result, inverter drive circuit 3 in FIG. 1 is referred to as inverter drive circuit 53 , and inverter apparatus 1 in FIG. 1 is inverter apparatus 51 .

In FIG. 5 inverter apparatus 51 comprises voltage inverter 2 and inverter drive circuit 53 . Inverter drive circuit 53 comprises high withstand voltage ICs 11 to 16 , clamp diodes D 11 to D 16 , dc supplies 22 and 31 to 36 , and protection circuits 61 to 66 .

Each protection circuit 61 to 66 is a circuit having a voltage-dividing resistor and parallel connected bypass diode, and in each protection circuit 61 to 66 a corresponding voltage dividing resistor R 61 to R 66 is parallel connected to a corresponding bypass diode D 61 to D 66 . As a result, because each protection circuit 61 to 66 has the same circuit configuration, the operation of protection circuit 63 is described below, and the operation of protection circuits 61 , 62 , and 64 to 66 is not described because it is the same as protection circuit 63 .

Protection circuit 63 is connected between low voltage side reference terminal VSS and external power supply terminal N of high withstand voltage IC 13 ; more specifically, the node between voltage dividing resistor R 63 and the anode of bypass diode D 63 is connected to low voltage side reference terminal VSS of high withstand voltage IC 13 , and the node between voltage dividing resistor R 63 and bypass diode D 63 is connected to external power supply terminal N.

Thus comprised, a reactor constituting a load is connected to external connection terminals U to W, and a negative surge caused between external connection terminal U and external power supply terminal N as a result of switching switching element Q 1 , for example, is voltage divided by resistance R 63 and clamp diode D 13 of protection circuit 63 . It should be noted that a circuit diagram excerpting the peripheral circuits of high withstand voltage IC 13 in FIG. 5 is the same as that shown in FIG. 2 except that protection circuit 21 is replaced by protection circuit 63 , and is described below referring to FIG. 2 and substituting protection circuit 63 for protection circuit 21 .

When the resistance of resistance R 63 is high, operating current I 1 of high withstand voltage IC 13 flowing from low voltage side reference terminal VSS to external power supply terminal N is limited by resistance R 63 , and operating current I 1 bypass flows through bypass diode D 63 parallel connected to resistance R 63 . It will be obvious that if the resistance of voltage-dividing resistance R 63 is low enough that it has no problem-causing effect on operating current I 1 , bypass diode D 63 can be omitted.

A corresponding protection circuit 61 to 66 is connected between each low voltage side reference terminal VSS and external power supply terminal N of high withstand voltage ICs 11 to 16 , and a closed loop to the ground line is formed by adding voltage-dividing resistance R 61 to R 66 in protection circuits 61 to 66 . Because this closed loop is related to improper operation of the high withstand voltage IC in some cases, a corresponding diode D 71 to D 76 can be connected as shown in FIG. 6 between the nodes between clamp diodes D 11 to D 16 and protection circuits 61 to 66 , and the low voltage side reference terminal VSS of the corresponding high withstand voltage IC 11 to 16 .

Using high withstand voltage IC 13 by way of example in FIG. 6, the anode of diode 73 is connected to low voltage side reference terminal VSS of high withstand voltage IC 13 , and the cathode of diode 73 is connected to the anode of clamp diode D 13 and the node between voltage dividing resistor R 63 and the anode of bypass diode D 63 . When thus comprised, formation of a closed loop from external-power supply terminal N through low voltage side reference terminal VSS to external power supply terminal N can be prevented, voltage fluctuation in low voltage side reference terminal VSS of high withstand voltage IC 13 resulting from a closed loop can be prevented, and improper operation of high withstand voltage IC 13 can be prevented. It should be noted that the other high withstand voltage ICs 11 , 12 , and 14 to 16 are the same, and description thereof is omitted.

Furthermore, depending upon the resistance of voltage-dividing resistance R 61 to R 66 , that is, if the resistance of voltage-dividing resistance R 61 to R 66 is low enough so that it has no problem-causing effect on operating current I 1 flowing from low voltage side reference terminal VSS to external power supply terminal N, bypass diodes D 61 to D 66 can be omitted as shown in FIG. 7 .

Furthermore, it should be noted that this second embodiment is described using by way of example a high withstand voltage IC for driving switching elements Q 1 to Q 6 , but as described in the first embodiment above the invention can be applied to a high withstand voltage IC used for switching element drive control, for example, a level shift circuit for driving a switching element and a high withstand voltage IC comprising a level shift circuit functioning as an overcurrent detection circuit for detecting overcurrent flow to a switching element.

As described above, an inverter apparatus according to a second embodiment of this invention disposes protection circuits 61 to 66 each having a parallel connected voltage dividing resistance and bypass diode between low voltage side reference terminal VSS of each high withstand voltage IC 11 to 16 and external power supply terminal N for applying a negative supply voltage to the voltage inverter 2 . It is therefore possible to prevent a negative voltage applied between the high voltage side reference terminal Vs and low voltage side reference terminal VSS of each high withstand voltage IC from dropping below the minimum rated withstand voltage between the terminals due to a negative surge produced when switching a switching element, and it is therefore possible to reliably prevent improper operation and withstand voltage breakdown of the high withstand voltage IC.

It should be noted that a case in which a resistor is used for the voltage-dividing resistance of the protection circuit is used in the above first and second embodiments, but the invention shall not be so limited and an inductance or other element effecting a voltage dividing resistance can be used. Furthermore, the above first and second embodiments have been described using a three-phase inverter apparatus by way of example, but the invention shall not be so limited and can obviously be applied to a single-phase inverter apparatus.

By adding a protection circuit of a simple configuration, the present invention can provide an inverter apparatus capable of preventing withstand voltage breakdown and improper operation of a high withstand voltage IC used for switching element drive control as a result of a negative surge produced when switching a switching element of the inverter.