Precision set-reset logic circuit and method

This application is a continuation of Ser. No. 09/456,748, filed Dec. 7, 1999, now U.S. Pat. No. 6,326,828.

1. Field of the Invention

This invention relates to SET-RESET latch circuits which produce logic latched outputs determined by SET and RESET inputs.

2. Description of the Related Art

Various types of circuits have been developed that produce and hold output states in response to input pulses. These include standard cell D-type flip-flop circuits with a clear (an example is the Motorola, Inc. MECL 10K circuit, described in MECL DATA by Motorola, Inc., 1996, page 1-5), the standard cell S-R (SET-RESET) latch (an example is described in Analog Devices, “ADRF ECL Cell Library Datasheet”, 1996, and the solid state integrated logic flipflop or S-R latch in Taub and Schilling, “Digital Integrated Electronics”, McGraw-Hill, Inc., 1977, pages 278-283.

Each of these circuits exhibits a degree of undesirable jitter and settling time in responding to control inputs. This lowers their bandwidth and makes the logic output lag undesirably behind the application of the control input.

This invention seeks to provide a precision SET-RESET logic circuit that produces a logic output whose rising and falling edges are defined precisely by the rising edges of its SET and RESET inputs, with a significant reduction in jitter and settling problems and an accompanying increase in bandwidth.

These goals are achieved by recognizing that the primary source of jitter and settling problems is in the storage element which provides a latch to maintain the output state of the S-R circuit after an input pulse has terminated. The invention removes the latch circuit from the critical signal path between the S-R inputs and the logic outputs, thus allowing for a very rapid logic response to a change in input, with the response sustained by the latch circuit once it has had an opportunity to reach a settled state. The latch circuit's signal path is longer than the input signal paths of the SET-RESET circuit.

In a preferred implementation, the SET-RESET circuit includes two pairs of primary differential switches and a secondary differential switch. The branches of the first primary switch are respectively controlled by SET and negated SET (SET′) inputs, while the branches of the second primary switch are respectively controlled by RESET and negated RESET (RESET′) inputs. The branches of the secondary differential switch provide current paths to control conduction through the first and second primary switches, respectively. SET and RESET outputs are produced in response to the application of SET and RESET inputs to the first and second primary differential switches, respectively.

The branches of the secondary differential switch respond respectively to LATCH and LATCH′ inputs from the separate latch circuit. Initial current paths are established through the primary and secondary switches that control the SET and RESET outputs before the latch circuit has time to respond. The latch circuit then holds these outputs by establishing a different current path through the primary and secondary differential switches. The latch circuit itself can be designed as a cross-coupled NOR circuit, preferably with single-ended ECL (emitter coupled logic) elements.

These and other features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings.

FIG. 1 is a simplified signal trace illustrating the circuit's response to various SET and RESET inputs;

FIG. 2 is a schematic diagram of one embodiment of the invention; and

FIG. 3 is a chart illustrating the logic states of various elements in FIG. 2 in response to SET and RESET inputs as illustrated in FIG. 1 .

The overall function of the new S-R logic circuit is summarized in FIG. 1 . Illustrative SET and RESET input signals are indicated by digital signal traces Sin and Rin, respectively, while the SET output is indicated by trace Sout; the RESET output Rout would be opposite to Sout. When a Sin pulse 2 appears, it very rapidly produces a corresponding Sout pulse 4 , with the rising edges of pulses 2 and 4 nearly coinciding. The Sout pulse 4 is latched at a logic HI even after Sin pulse 2 has terminated, and does not revert to a logic LO until a RESET Rin pulse 6 appears. The logic LO state 8 for Sout is then latched beyond the termination of Rin pulse 6 until the appearance of the next Sin pulse 10 , at which time Sout again goes to a HI state in pulse 12 .

Assume next that another Rin pulse 14 appears before the termination of Sin pulse 10 . The S-R circuit can be set up so that either the SET or RESET pulse dominates the output when both inputs are present. In this example the Rin pulse dominates, causing Sout to go LO when Rin pulse 14 first appears. This LO state 16 for Sout is latched through the next set of input pulses, illustrated as the simultaneous application of Sin pulse 18 and Rin pulse 20 , again on the assumption that a RESET dominant circuit configuration has been selected. Sout enters a HI output state 22 when Rin pulse 20 terminates, since Sin pulse 18 continues beyond the termination of pulse 20 . With the circuit set up so that the last input pulse to be released takes precedence over the output, the HI Sout pulse 22 continues HI after Sin pulse 18 terminates.

This general logic pattern is not novel, but has been described to put the invention in context. The input pulses Sin and Rin and output pulses Sout are illustrated as having very rapidly rising leading edges. In practice, however, the pulse characteristics have not been so ideal with past S-R logic circuits. Due to delays and signal processing effects within the logic circuitry, there have been transitory ambiguities as to the presence or absence of an input pulse. The result has been not only an undesirable lag in the production of a true output, but also the possibility of false outputs. For example, if the logic circuitry allows for an input pulse with a rapidly rising leading edge that oscillates or is otherwise lacking in smoothness, a drop in the SET input pulse might be interpreted as the application of a RESET input pulse, resulting in a false RESET output. If, on the other hand, the logic circuitry produces a smoothly rising leading edge for an input pulse, this stretches out the period before the pulses reaches its full value, leading to a degree of uncertainty as to when the pulse actually commenced and the possibility of missing a SET output entirely if a RESET input pulse arrives before a SET input has been applied long enough to produce a SET output.

The invention recognizes that such distortions to the input pulses are largely a result of the latch circuitry that is conventionally used to store the last output state after the initiating input pulse has terminated. The problem is resolved by removing the latch circuitry from the critical input-output logic signal path. This allows for a very rapid and accurate logic response to an input pulse, followed by a signal latching action that can still be subject to the defects found in-the prior art. However, since the latch circuit is out of the critical logic signal path, these deficiencies do not degrade the logic output. The logic circuitry will normally have time to operate before an input pulse terminates or an opposite input is applied, so that the lag in establishing a latch will not detract from the circuit's desired operation.

A circuit that can be used to implement the invention is shown in FIG. 2 . It has two principal subcircuits: an S-R logic circuit 24 that provides the basic logic response to SET and RESET input signals, and a latch circuit 26 that is outside of the direct input-output signal path for the logic circuit 24 and has a slower response.

The latch circuit 26 can be implemented as a cross-coupled NOR circuit which produces latch (L) and negated latch (L′) outputs in response to input SET (Sin), negated SET (Sin′), RESET (Rin), and negated RESET (Rin′) signals. The circuit preferably uses single-ended emitter coupled logic (ECL) gates, which produce relatively clean outputs. The Sin and Sin′ inputs are applied to a buffer B 1 , which converts the differential SET input to a single-ended input to a first OR gate OR 1 . Similarly, Rin and Rin′ are applied to another buffer B 2 and converted to a single-ended input to another OR gate OR 2 . OR 1 and OR 2 are cross-coupled, yielding an overall NOR gate whose outputs L and L′ are taken from the true and negated outputs of OR 1 , respectively. This results in a RESET dominance for the overall S-R circuit, and a SET dominance for the latch circuit. If SET dominance is desired for the overall S-R circuit (the choice is somewhat arbitrary), the output from the NOR gate could be taken from the outputs of OR 2 instead. A dummy OR gate OR 3 receives inputs from the true outputs of OR 1 and OR 2 to equalize the loadings on their dual outputs.

The main S-R circuit 24 is shown implemented with npn bipolar transistors and power supply voltage references of ground and −Vee (typically −5.2 volts). Other transistor types could also be employed, such as pnp bipolar transistors with a positive voltage supply, or field effect transistors (if their lower speed would be acceptable).

In the particular circuit shown, no signals swing from ground to −Vee. All signals swing typically 300 mV. For differential signals such as Sin and Sin′, the signal that is the higher of the two is considered to be a logic HI, and the lower of the two is considered to be a logic LO. For single-ended signals, such as those present in the latch circuit, if a signal is well above the level of the latch bias it is at a logic HI; if it is below the latch bias, it is at a logic LO.

The logic circuit 24 includes a pair of primary differential switches Q 1 -Q 2 and Q 3 -Q 4 , whose bases are respectively connected to receive Sin, Sin′, Rin′, and Rin as inputs. A secondary differential switch consisting of transistors Q 5 and Q 6 controls the flow of current through the two primary differential switches, with the collector of Q 5 connected to the common emitter connection for Q 1 and Q 2 , and the collector of Q 6 connected to the common emitter connection for Q 3 and Q 4 . The conduction of Q 5 and Q 6 in turn is controlled by the latch outputs L′ and L, respectively. This is accomplished by applying L′ to the base of a transistor Q 7 whose collector-emitter circuit is connected between ground and the base of Q 5 , and L to the base of a transistor Q 8 whose collector-emitter circuit is connected between ground and the base of Q 6 . When L is applied, indicating the presence of an Sin signal at the input to the latch circuit 26 , the emitter of Q 8 is set to a voltage higher than the emitter of Q 7 (typically 300 mV). Hence the base of Q 6 is at a higher voltage than the base of Q 5 . This turns Q 6 ON and allows current to flow through the Q 3 -Q 4 primary differential switch. At the same time, Q 5 turns OFF because its base voltage is at a lower potential than the base of Q 6 , thus preventing any current flow through the first primary differential switch Q 1 -Q 2 .

Conversely, when Rin and Sin′ are applied to the latch circuit 26 to produce an L′ output, Q 5 turns ON to allow conduction through the Q 1 -Q 2 differential switch, while Q 6 turns OFF to inhibit current flow through the Q 3 -Q 4 differential switch. Q 5 /Q 7 and Q 6 /Q 8 thus function as current control circuits for the first and second differential switches, respectively.

The logic circuit 24 operates to produce an Sout output in response to Sin and Rin′ inputs, and (because of the S-R circuit's overall RESET dominance) an Rout output in response to Rin together with either Sin or Sin′ inputs. In the particular embodiment shown, this is achieved by connecting a first resistor R 1 between the ground reference and the collectors of Q 1 and Q 3 , a second resistor R 2 between the ground reference and the collectors of Q 2 and Q 4 , and deriving the S-R circuit outputs from the current flows through R 1 and R 2 . This takes place via a pair of transistors Q 9 and Q 10 whose bases are connected respectively to the opposite sides of resistors R 1 and R 2 from the ground reference, with their collectors connected to the ground reference, and a second pair of transistors Q 11 and Q 12 whose bases are connected respectively to the emitters of Q 9 and Q 10 , with their collectors connected to the ground reference and their emitters connected respectively to the Rout and Sout output nodes. A bias circuit is provided by transistors Q 13 , Q 14 , Q 15 , Q 16 , Q 17 , Q 18 , and Q 19 , all of which are biased by a common base voltage Vb, with their collectors connected respectively to the emitters of Q 5 /Q 6 , Q 7 , Q 8 , Q 9 , Q 10 , Q 11 , and Q 12 , and their emitters connected to −Vee respectively through bias resistors R 3 , R 4 , R 5 , R 6 , R 7 , R 8 , and R 9 . Acceptable resistance values are 1.25 kohm for R 1 -R 3 , R 8 , and R 9 , and 5.0 kohm for R 4 -R 7 .

Q 9 -Q 12 are configured as emitter-followers and act as unity gain buffers. Their main purposes are to provide a low impedance drive on the output node (much lower than the impedance of R 1 and R 2 would provide), and to provide level translation. Low impedance is important to enable the circuit to drive parasitic and load capacitances without significant signal degradation. Each emitter-follower imparts a 1 Vbe level shift drop in the output voltage.

Note that the input signal paths for Sin, Sin′, Rin′ and Rin to input transistors Q 1 -Q 4 are always shorter than the signal paths of the same input signals through the latch circuit. Thus, the latch response time to Sin and Rin is always longer than the response time of the primary differential switches. This allows the logic circuit to react very rapidly to a change in input signals, followed by the latch circuit operating to latch the new logic state. Thus, the overall circuit achieves the stability of a latch that maintains a fixed logic state, but without the sacrifice in speed that normally accompanies a latch function.

FIG. 3 summarizes the response of the FIG. 2 circuit to the first several pulses illustrated in FIG. 1 . Assume that initially, immediately prior to the application of Sin pulse 2 , both Sin and Rin are at a logic LO, with the latch outputs L at logic LO and L′ HI. As indicated on the “INITIAL” line of FIG. 3, this causes the Q 1 branch of the first primary differential switch to be OFF and the Q 2 branch ON, the Q 3 branch of the second primary differential switch ON and the Q 4 branch OFF, and Q 5 in the secondary differential switch ON with Q 6 OFF. A current path is thus established through Q 2 and Q 5 that draws current through R 2 , producing a voltage drop across R 2 to lower the base voltage of Q 10 , resulting in the voltage at the base of Q 12 being lowered by an equal amount (the transistors included in the current path are circled in FIG. 3 ). This in turn lowers the voltage at Sout to a logic LO, i.e. Sout is lower in potential than Rout. Q 1 and Q 6 both being OFF prevents any current flow through R 1 , which sets the base voltage of Q 9 at the high reference ground, setting the base of Q 9 higher than the base of Q 10 . As a result, the base of Q 11 is also higher than the base of Q 12 . Hence, the voltage at Rout is greater than the voltage at Sout, indicating that Rout is a logic HI and Sout is a logic LO.

When the Sin pulse 2 is first applied (“Sin 2 APPLIED” in FIG. 3 ), the transistors in the Q 1 -Q 2 primary differential switch change state, with Q 1 turning ON and Q 2 OFF. The RESET inputs remain unchanged, so Q 3 remains ON and Q 4 OFF. Also, since the latch circuit 26 has not had enough time to respond when Q 1 and Q 2 first respond to the Sin signal, L remains LO and L′ remains HI, keeping Q 5 ON with Q 6 OFF. Thus, the previous current path through Q 2 and Q 5 is terminated and a new current path through Q 1 and Q 5 is established. R 1 is thus included in the main current path, while no current can flow through R 2 . This reverses the relative voltage levels and hence the logic states of Q 9 -Q 12 , resulting in Sout going HI and Rout going LO.

The latch circuit 26 next completes its response to the Sin signal, placing the L output HI and L′ LO (shown on the first “LATCH RESPONDS” line of FIG. 3 ). Since Sin and Rin have not changed, the switching states of Q 1 -Q 4 remain the same. However, since L and L′ have changed states, the switching states of Q 5 and Q 6 also reverse. This opens a new current path, through Q 3 and Q 6 , which maintains the current flow through R 1 , latching Sout HI and Rout LO.

The latch remains in place after Sin pulse 2 has terminated (“SET REMOVED” in FIG. 3 ), which maintains the current path through Q 3 and Q 6 , thus holding the latch on the Sout and Rout outputs. Although Q 1 and Q 2 have reversed switching states from the removal of Sin, this has no effect on Sout and Rout because Q 1 and Q 2 are not included in the through current path. In the absence of Sin and Rin, the latch retains its most recent state.

Assume now that Rin pulse 6 is applied (“Rin 6 APPLIED” in FIG. 3 ). This causes Rin to be HI but does not change L or L′, resulting in a current path through Q 4 and Q 6 that sets Sout LO and Rout HI. When the latch circuit has had time to respond (second “LATCH RESPONDS” in FIG. 3 ), setting L LO and L′ HI, the current path switches to Q 2 and Q 5 but current still flows through R 2 , latching Sout LO and Rout HI. At the conclusion of Rin pulse 6 (“Rin REMOVED” in FIG. 3 ), Rin goes LO, reversing the switching states of Q 3 and Q 4 . However, this does not disturb the current path through Q 2 and Q 5 , so the outputs Sout and Rout remain latched in the their LO and HI states, respectively.

When Sin pulse 10 is applied (“Sin APPLIED”); the circuit responds the same as it did to Sin pulse 2 , both before and after the latch circuit has had time to operate. Rin pulse 14 is then applied (“Rin 14 APPLIED”), reversing the conductive states of Q 3 and Q 4 so that Q 3 is OFF and Q 4 ON. The current path is now through Q 4 and Q 6 , which sets Sout LO and Rout HI. The overall logic circuit is thus seen to be RESET dominant; RESET dominates when both SET and RESET signals are applied. The latch circuit 26 in this particular implementation is SET dominant, so that the latch outputs do not change when the latch circuit has responded (third “LATCH RESPONDS” in FIG. 3 ), L remaining HI and L′ remaining LO. All of the transistor states thus remain the same, with Sout latched LO and Rout latched HI.

The termination of Sin pulse 10 (“Sin 10 REMOVED”) reverses the conductive states of Q 1 and Q 2 . However, this has no effect on Sout and Rout, since the current path initially remains through Q 4 and Q 6 . However, the latch circuit responds to the removal of Sin pulse 10 (fourth “LATCH RESPONDS”) by setting L LO and L′ HI, since the reset pulse 14 is still being applied. This reverses the switching states of Q 5 and Q 6 , turning Q 5 ON and Q 6 OFF. But Sout and Rout remain respectively LO and HI, since a new current path is established through Q 2 and Q 5 that maintains the current transmitted through R 2 by the immediately prior Q 4 -Q 6 current path. This is consistent with the RESET dominant nature of the overall logic circuit.

Finally, Rn pulse 14 terminates (“Rin 14 REMOVED”), causing the conductive states of Q 3 and Q 4 to reverse. But this does not effect the current path through Q 2 and Q 5 , so Sout remains LO and Rout remains HI. The latch circuit maintains the latched outputs L LO and L′ HI, thus maintaining Sout LO and Rout HI.

It can thus be seen that, when the logic outputs Sout and Rout change in response to a changed input that shifts the current flow between R 1 and R 2 , the latch operates to maintain the changed output by establishing a new current path to keep the current flow through the new resistor. This allows for a rapid response by the logic circuit without the output aberrations normally associated with a latch function.

While a particular illustrative embodiment of the invention has been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. It is therefore intended that the invention be limited only by the appended claims.