Method of fabricating semiconductor wafers having multiple height subsurface layers

This invention relates generally to the use of semiconductor substrates and more specifically to an improved method of fabricating a substrate having regions of varying height.

Semiconductor wafers can be formed in many shapes for a variety of uses. One important practical application for semiconductor substrates is in the fabrication of micro-electro-mechanical systems (MEMS) in the form of electrostatic actuators. In such devices and in other applications, it may be useful to have regions of the semiconductor with varying heights. Design flexibility is significantly increased by the ability to shape the semiconductor wafer. For example, when a fabricated silicon wafer is used as the substrate of an electrostatic actuator the electric field force can vary substantially due to the shape of the substrate.

Using current semiconductor fabrication processes, it is difficult to form a substrate having regions of varying height. Typically a semiconductor wafer, for example a silicon wafer, is fabricated through a process that includes deposition, masking, and etching. Deposition may include depositing a protective layer on top of the silicon substrate. The protective layer may be, for example, silicon dioxide, silicon nitride, a polymer, or other like material. The protective layer may be deposited or may be formed upon the substrate.

Masking includes placing a pattern upon the protective layer in a stencil-like fashion. The wafer is then selectively etched through an etching process that may be, for example, a reactive ion etching process or a wet chemical etching process, or some other etching process known in the art. The selective etching of the silicon wafer creates a structure as determined by the pattern as described above.

Typically the wafer is etched straight down. This process limits the design flexibility in terms of the shape of the fabricated wafer. That is, the three-dimensional structure created is a projection of the pattern. Typically, fabrication of wafers is done as a batch process. This allows a thousand, or more, devices to be fabricated at a time from a single large wafer. Throughout the process there is no physical machining of the wafer surface, no tools touch the wafer. It is not practical to address each device on the wafer, instead the entire wafer is subjected to the process described above. The sequence of operations of the process must be tailored to produce the desired device shape.

Using the method as described above it is difficult to vary the size of portions of the wafer. Methods such as undercutting or inverting the wafer provide a limited ability to vary the height of portions of the substrate, thus providing only minimal increase in design flexibility.

A method is disclosed for creating a subsurface patterned layer and exposing the subsurface patterned layer to further processing. A first protective layer is formed upon a first substrate layer. The first protective layer is then selectively patterned such that patterned portions of the first protective layer are reduced. A second substrate layer is then bonded to the first protective layer such that a subsurface patterned layer is formed. A second protective layer is formed upon the second substrate layer and the second protective layer is then selectively patterned such that portions of the second substrate layer are exposed. The exposed portions of the second substrate layer are then etched such that the subsurface patterned layer is exposed.

Other features and advantages of the present invention will be apparent from the accompanying drawings, and from the detailed description, that follows below.

The present invention is illustrated by way of example, and not limitation, by the figures of the accompanying drawings in which like references indicate similar elements and in which:

FIG. 1 illustrates a process flow diagram according to one embodiment of the present invention;

FIGS. 2A through 2I illustrate the fabrication of a multiple depth structure according to one embodiment of the present invention; and

FIGS. 3A through 3C illustrate examples of alternative embodiments of the process of the present invention.

A method is described for fabricating semiconductor wafers having portions of varying height. The method includes patterning a semiconductor substrate and bonding to it one or more other patterned substrates creating a subsurface patterned layer. The subsurface patterned layer is then exposed for selective processing. For example, the layered structure may then be repeatedly etched to produce a multiple depth structure. This method of fabrication provides substantial advantages over previous methods.

An intended advantage of one embodiment of the present invention is to provide multiple depth semiconductor structures for use in MEMS devices. Another intended advantage is to provide and simplify the fabrication process of high resolution multiple depth structures. Another intended advantage is to allow the masking process for a subsurface feature to be effected upon a planar surface. Another intended advantage is to provide reliable bonding of semiconductor wafer layers. Another intended advantage is provide more uniform structures through the use of stop layers to address non-uniformities in the fabrication process.

As described in more detail below, one embodiment of the present invention is a method of fabricating semiconductor substrates having portions of varying height, i.e., multiple depth structures.

FIG. 1 is a process flow diagram according to one embodiment of the present invention. The process 100 , shown in FIG. 1 begins at operation 105 in which a protective layer is formed or deposited upon a first substrate layer. In a preferred embodiment the substrate may be a semiconductor wafer, for example, a silicon wafer. In alternative embodiments the substrate material may be some other semiconductor material such as gallium arsenide, or may be glass or metal. In a preferred embodiment, the protective layer may be an oxide layer formed upon the substrate layer.

At operation 110 the protective layer is selectively patterned. The pattern depends upon the desired application. In a preferred embodiment the patterning may be accomplished through the deposition of a photosensitive layer that is then selectively exposed to light. The areas exposed to light are then removed through a development process. This leaves an opening in the photosensitive layer exposing a portion of the protective layer. The exposed portion of the protective layer is then etched (for example by a reactive ion etching process) thereby reducing the protective layer thickness in the exposed regions.

At operation 115 a second substrate layer is bonded to the patterned protective layer of the first substrate. In an alternative embodiment the second substrate layer may be deposited upon the first substrate layer. The second substrate layer may be the same material as the first substrate or may be another material or combination of material. A protective layer is formed or deposited upon the second substrate layer at operation 120 and the second substrate is selectively patterned at operation 125 .

At operation 130 the second substrate layer is etched. The etching may be accomplished using one or more standard etching processes well known to those skilled in the art. For example, the etching may be a dry etching process such as reactive ion etching (RIE), or could be a wet chemical etching process. The patterned protective layer protects the substrate material below it and the exposed material is etched away. The etching of the second substrate layer exposes the patterned protective layer of the first substrate layer.

At operation 135 the patterned protective layer of the first substrate is subjected to etching. This may involve a two-part etching process. A first etch may be used to remove any residual protective material (e.g., oxide) from the patterned areas. A second etch may then be used to etch the exposed substrate material of the first substrate layer thus creating a structure of varying height.

In an alternative embodiment, the top side and back side of the second substrate is patterned to provide better alignment between the two patterned layers.

FIGS. 2A through 2I illustrate the fabrication of a multiple depth structure according to one embodiment of the present invention. FIG. 2A shows a substrate 201 that may be a semiconductor (e.g., silicon). The substrate may be other materials as well, such as glass or metal.

FIG. 2B shows the addition of a protective layer 202 . In a preferred embodiment this protective layer may be a layer of silicon dioxide formed by subjecting a silicon substrate to heat and gases. In alternative embodiments the protective layer 202 may be other materials, and may be deposited upon the substrate 201 . The protective layer 202 may be chosen for its mechanical or electrical characteristics depending upon the application.

FIG. 2C shows the protective layer 202 after a patterning and etching process. Patterning may typically be accomplished by applying a photosensitive layer, not shown, to protective layer 202 . A stencil of the desired pattern may then be placed upon the photosensitive layer and light is applied. The material exposed to the light is then typically removed using an etching process. The stenciled pattern is impervious to the etching thereby leaving a stenciled pattern on protective layer 202 . In a preferred embodiment, a thin portion 202 a of protective layer 202 remains after the etching process. This thin portion 202 a may function as an etch stop as described below in reference to FIG. 2 G. In an alternative embodiment thin portions 202 a may not used, leaving the substrate layer 201 exposed.

FIG. 2D shows the addition to the structure of a substrate layer 203 . The substrate layer 203 may be the same material as the substrate layer 201 , or may be a different material. Substrate layer 203 is bonded to the patterned side of protective layer 202 . This creates a patterned subsurface layer that can be selectively processed when it is later exposed as described below. Protective layer 202 has a relatively planar surface that allows for a reliable bonding process.

FIG. 2E shows the combined substrates with an additional protective layer 204 . Typically, for a silicon substrate, the structure is re-oxidized forming a layer upon the exposed substrate layer (i.e., substrate layer 203 ). The oxidation process is typically effected upon the entire structure. but adds only negligibly to the previous oxidation layer (i.e., protective layer 202 ). The protective layer 202 acts as insulation to further oxidation.

FIG. 2F shows protective layer 204 after a patterning and etching process. This process may be the same as that described above in reference to FIG. 2C or may another patterning and etching process. Some portion of the protective layer 204 has been removed so that etching of the substrate layer 203 can be effected.

FIG. 2G shows the result of the etching of the substrate layer 203 . The directional etching etches vertically down and removes exposed portions of the substrate layer 203 . The remaining portion of the protective layer 204 protects that portion of substrate layer 203 that is directly below it. The etching continues until the protective layer 202 is reached. Thin portions 202 a act as an etch stop protecting the substrate layer 201 . In practice the etching is not uniform, the etching is accelerated in the middle as compared with the edges. When the etch encounters thin portions 202 a the etching in that area is stopped while the etching continues at the edges. This results in the uniform etching of substrate layer 203 .

FIG. 2H shows the removal of thin portions 202 a of protective layer 202 . To remove thin portions 202 a, a different etch may be used that can etch the protective layer. For example, an etch is used that can etch silicon dioxide. This etching process may remove some of the exposed patterned portion of protective layer 202 while removing thin portions 202 a. At this point the buried patterned surface, as described above in reference to FIG. 2D, is exposed.

FIG. 2I shows the multiple level structure resulting from a final etching process. This etching process may be the same as that described above in reference to FIG. 2G, or may a different etching process.

FIGS. 3A though 3 C show examples of alternative embodiments of the process of the present invention.

FIG. 3A shows a structure in which the final etching process, described in reference to FIG. 21 is not used to create a multiple level structure. Instead of the final etching process that would etch away exposed portions of substrate layer 201 , a process is used to build up the exposed portions of substrate layer 201 . The additional material 101 a added to substrate layer 101 may be the same as the material of substrate layer 101 or may be another material that adheres to the material of substrate layer 101 . For example, if substrate layer 101 is silicon, the additional material 101 a may be silicon or a metal such as tungsten that adheres to silicon, but not to silicon dioxide. The additional material 101 a may be applied using an electroplating process, an electroless deposition or some other process.

FIG. 3B shows an exemplary structure using a different pattern than the one described in reference to FIG. 2 F. This structure illustrates that the patterning process can be varied to form a variety of structure shapes.

FIG. 3C shows an exemplary structure created by reiterating the process of the present invention and varying the patterns. This structure illustrates that the process may be repeated to create structures having several different heights.

The method of the present invention may be applied to a variety of MEMS devices including micro-fluidic devices, inertial sensors, and RF devices, among others.

In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.