Power device driving circuit and associated methods

This application is based upon prior filed copending provisional application No. 60/221,700 filed Jul. 31, 2000, the entire disclosure of which is incorporated herein by reference.

The present invention relates to integrated circuits, and more particularly, to circuits for driving power devices including voltage level shifters.

Power conversion control circuits often use voltage level shifter circuits to translate input logic voltage level signals operating at low voltages (e.g. “low side” at 5 to 12 volts) to output signals at higher voltage levels (e.g. “High side” at 100-112V). For example, automotive, electronic data processing, and industrial control applications require high voltage level shifter circuits to drive various peripheral devices. Such circuits are often implemented in application specific integrated circuits (ASICs) or as independently packaged circuits. Voltage level shifter circuits are usually implemented with logic level devices, fabricated using metal oxide semiconductor field effect transistors (MOSFETS).

Voltage level shifter circuits normally receive an input signal and output an output signal at a different voltage than the input signal. Ideally, voltage level shifter circuits should draw no DC current from the power supplies used to determine the desired output voltages. The output voltages attainable are a function of the power supplies to the shifter circuit and the capabilities of the devices used to build the circuit.

As mentioned, voltage level shifter circuits translate a logic level input signal to signals at high voltage levels. This is a common need in half and full bridge drivers. Conventional approaches send a continuous or pulsed current signal to one high side node to signal a logic “0” state, or a continuous or pulsed current signal to a second high side node to signal a logic “1” state. When the current signal flows, it flows from the high side voltages to the low side voltages, which can be many hundreds of volts differential, limited only by the breakdown voltage of the transmitting/receiving devices. Accordingly, when this current flows across these large voltages, relatively high power dissipation occurs.

In view of the foregoing background, it is therefore an object of the invention to provide a circuit and method for translating a logic level input signal to signals at high voltage levels to drive a power device, such as a power MOSFET, while minimizing the power consumption.

This and other objects, features and advantages in accordance with the present invention are provided by a high side gate driver. The high side gate drive includes a high side gate driver logic input, a high side gate driver output, a latch connected between the high side gate driver logic input and the high side gate driver output, and a control circuit receiving an output of the latch and controlling signals from the high side gate driver logic input to the latch based upon the output of the latch.

Preferably, the high side gate driver further comprises first and second level shifting signal paths connecting the high side gate driver logic input and the latch. A first switch is in the first level shifting path between the high side gate driver logic input and the latch controlled by the output of the latch, and a second switch is in the second level shifting path between the high side gate driver logic input and the latch controlled by an inverted output of the latch. The first and second switches may comprise P-channel pass transistors. Also, the high side gate driver may include a high side floating voltage supply, and respective loads, such as resistors, connecting the first and second level shifting signal paths to the high side floating voltage supply.

The high side gate driver may also comprise a first current source in the first level shifting path controlled by the high side gate driver logic input, and a second current source, out of phase with the first current source, in the second level shifting path controlled by the high side gate driver logic input. As such, the first and second current sources may comprise respective out of phase NMOS pass transistors controlled by the high side gate driver logic input and connected to a reference voltage supply. Additionally, the latch may be an active low SR latch.

Objects, features and advantages in accordance with the present invention are also provided by a method for driving the power device including latching a high side gate driver logic input signal with a latch, outputting a high side gate driver output signal based upon the latched high side gate driver logic input signal, and controlling the high side gate driver logic input signal based upon the high side gate driver output signal to minimize power consumption. Controlling the high side gate driver logic input signal preferably comprises controlling first and second level shifting signal paths connecting a high side gate driver logic input and the latch. Again, switches, such as P-channel pass transistors, in the level shifting paths between the high side gate driver logic input and the latch are controlled by an output of the latch.

Controlling the first and second level shifting signal paths may further include connecting respective loads, such as resistors, between the first and second level shifting signal paths and a high side floating voltage supply, and providing current sources, such as respective out of phase NMOS pass transistors, in the level shifting paths controlled by the high side gate driver logic input.

FIG. 1 is a schematic block diagram of a circuit for driving a power device according to the present invention.

FIG. 2 is a schematic diagram of the high side gate driver of the circuit for driving the power device of FIG. 1 .

FIG. 3 is a more detailed schematic diagram illustrating an embodiment of the high side gate driver of FIG. 2 .

The present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.

Referring to FIG. 1, a circuit 10 for driving a power device, such as a power MOSFET, will now be described. The circuit 10 is preferably a half or full bridge driver and includes a high side gate driver 20 and a low side gate driver 30 which are independently controlled. The circuit 10 has various voltage supplies and logic inputs/outputs. These include logic supply VDD, logic ground VSS, high side floating supply VB, high side floating supply return VS, high side gate driver logic input HIN, shutdown logic input SD, low side gate driver logic input LIN, high side gate driver output HO and low side gate driver output LO.

The high side gate driver 20 will now be described with reference to FIGS. 2 and 3. A general embodiment of the high side gate driver 20 includes a latch 22 which latches and outputs the high side gate drive output signal HO. A first level shifting current path includes a current source SW 2 , transistor M 1 , node N 1 and load ZL 1 connected to the high side floating supply VB. A second level shifting current path includes a current source SW 4 , transistor M 3 , node N 2 and load ZL 2 connected to the high side floating supply VB. The latch 22 receives signals from nodes N 1 and N 2 in the respective current level shifting paths. The current sources SW 2 and SW 4 are out of phase with each other (i.e. one on, the other off) and are controlled by the high side gate driver logic input HIN. Transistors M 1 and M 3 are preferably P-channel pass transistors in the level shifting current paths which are controlled by fedback outputs of the latch 22 .

In the example illustrated in FIG. 3, the out of phase current sources SW 2 and SW 4 are implemented by out of phase NMOS pass transistors M 2 and M 4 connected to logic ground VSS (0 volts). These transistors M 2 and M 4 are controlled out of phase by the high side gate driver logic input HIN and the inverter 24 . The loads ZL 1 and ZL 2 are implemented by resistors R 1 and R 2 and the latch is an active low SR latch. The logic supply VDD is 12 volts, the high side floating supply VB is 112 volts, and the high side floating supply return VS is 100 volts, for example.

In operation, if the high side gate driver logic input HIN equals “0”, then transistor M 2 is off and transistor M 4 is on. If the high side gate drive output HO equals “1” (i.e. the wrong state as HO=HIN=0 is desired), then the transistor M 1 is off and transistor M 3 is on (as M 3 is controlled by Q\=0). With both transistors M 3 and M 4 on, they conduct and a voltage drop is seen across resistor R 2 . The transistor and resistor sizes are selected so that this voltage drop appears as a logic “0” at the R\ input of the latch 22 which then resets the latch and outputs Q=0 and Q\=1.

With Q\ now equal to “1”, transistor M 3 shuts off and stops the current flowing in the second level shifting current path M 4 -M 3 -N 2 -R 2 . It should be noted that with Q now equal to “0”, the transistor M 1 turns on but transistor M 2 is still off and thus no current flows in the first level shifting current path M 2 -M 1 -N 1 -R 1 . As soon as the high side latch 22 is switched to the correct state (e.g. HO=HIN=0) the conducting current path is shut off.

Similarly, if the high side gate driver logic input HIN is switched to “1”, transistor M 2 turns on, transistor M 4 turns off and the first level shifting current path M 2 -M 1 -N 1 -R 1 is conductive until the voltage drop across resistor R 1 sets the latch at Q=1, and Q\=0. Then transistor M 1 shuts off the high to low side current flow. Transistor M 3 turns on when transistor M 1 turns off but no current flows in the second level shifting current path M 4 -M 3 -N 2 -R 2 because transistor M 4 is off. Again, the high to low side current flow is only maintained until the latch reaches the correct state, then current flow is shut off.

The loads ZL 1 and ZL 2 could be implemented with other devices such as gain controlled current mirrors, for example. Of course current sources SW 2 and SW 4 could also be implemented in many different ways as would be appreciated by the skilled artisan. Almost any type of latch 22 could be used provided the feedback connections are properly routed to shut off current flow when the latch reaches the correct state.

The switching of large voltages can couple large currents into junction and stray capacitances, resulting in false level shifting current signals. As such, noise cancellation circuitry would also be appropriate. Also, parallel redundant level shifting current paths could be used to obtain immunity from single event upset (SEU)

Conventional approaches send a continuous or pulsed current signal to one high side node to signal a logic “0” state, or a continuous or pulsed current signal to a second high side node to signal a logic “1” state. The invention sends a pulsed signal to one or the other of the two high side nodes but can sense when the signal has been recognized by the high side logic, and then shuts off the current pulse. This minimizes the power used. When the current signal flows, it flows from the high side voltages to the low side voltages, which can be many hundreds of volts differential, limited only by the breakdown voltage of the transmitting/receiving devices. Accordingly, when this current flows across these large voltages, relatively high power dissipation occurs. The invention minimizes this power by shutting off the current flow as soon as the signal has been recognized by the high side logic.

Many modifications and other embodiments of the invention will come to the mind of one skilled in the art having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is understood that the invention is not to be limited to the specific embodiments disclosed, and that modifications and embodiments are intended to be included within the scope of the appended claims.