Magnetic recording writing circuit

The present invention relates to a writing circuit in a magnetic recording apparatus such as a hard disk drive (HDD) or a floppy disk drive (FDD) drive. More particularly, this invention relates to a magnetic recording writing circuit which can arbitrarily control the waveform of a write current in writing.

FIG. 4 is a circuit diagram of a conventional writing circuit in a magnetic recording apparatus. An arrangement of the circuit will be explained below.

As shown in FIG. 4, head 1 of this magnetic recording apparatus incorporates an equivalent circuit including inductance L 1 , resistor R 1 , capacitor C 1 , and resistor R 3 for reducing the impedance at a resonance frequency of the head 1 .

I 1 denotes a reference current source for supplying a reference current for a write current Iw. The reference current source I 1 is connected at one terminal to the collector of an NPN transistor Q 1 and the base of another NPN transistor Q 2 . The base of the NPN transistor Q 1 is connected to the emitter of the NPN transistor Q 2 and the base of a further transistor Q 16 . The collector of the NPN transistor Q 2 as well as the other terminal of the current source I 1 are connected to a third power source V 3 . The emitter of the NPN transistor Q 1 and the emitter of the NPN transistor Q 16 are connected to a second power source V 2 via two resistors R 4 and R 5 respectively.

The collector of the NPN transistor Q 16 is connected to the emitters of two NPN transistors Q 17 and Q 18 which are in turn connected at their collectors to the emitters of two transistors Q 19 and Q 20 respectively. The collectors of the two transistors Q 19 and Q 20 are connected to a first power source V 1 . Connected between the collectors of the two transistors Q 17 and Q 18 is the head 1 .

The bases of the transistors Q 17 , Q 18 , Q 19 , and Q 20 are connected to four terminals J, K, L, and M respectively.

Because of a current mirror function in FIG. 4, the collector of the NPN transistor Q 16 receives a current I 5 which is proportional to the transistor size of both the NPN transistors Q 1 and Q 16 at the reference current I 1 .

FIG. 5 illustrates the waveforms of input voltages at the terminals J, K, L, and M and the waveforms of corresponding currents I 2 , I 3 , I 4 , I 5 , and Iw.

During the period T 9 , the terminals K and L are fed with signals having low logical level and the terminals J and M are fed with signals having high logical level. This switches the NPN transistors Q 19 and Q 18 off and the NPN transistors Q 17 and Q 20 on. Accordingly, during the period T 9 , the current running from the source V 1 is passed through the NPN transistor Q 20 and turned to Iw in the head 1 and the current I 3 is passed through the NPN transistor Q 17 and turned to I 5 .

During the next period T 10 , the current from the source V 1 is passed through the NPN transistor Q 19 so the current Iw in the head 1 runs in a reverse of the direction in T 9 . The current I 2 is passed through the NPN transistor Q 18 and turned to I 5 .

The current Iw in the head 1 has a waveform shown in FIG. 5 because of the action of inductance L 1 , parasitic capacitance C 1 , resistance R 1 , and damping resistance R 3 . More specifically, the waveform includes an overshoot at the rise a 7 and its recovery a 8 before the normal write signal period at one polarity and another overshoot at the fall a 9 and its recovery a 10 before the normal write signal period at the other polarity.

In the conventional magnetic record writing circuit, such various time factors of the current Iw or the write current for magnetic recording, which include the rise speed and overshoot at each rise a 7 , overshoot recovery a 8 , fall speed and overshoot at each fall a 9 , and overshoot recovery a 10 , can hardly be controlled.

While an arrangement for increasing the write current with a fixed level at the rise is disclosed in U.S. Pat. No. 5,869,988, no attempt has been successfully made to provide a magnetic recording writing circuit controlling the overshoot and the overshoot recovery and modifying the current in response to a change in the reference current I 1 .

It is an object of this invention to provide a magnetic record writing circuit which can control the rise and fall of a write current to minimize the write time and the overshoot period.

In the magnetic record writing circuit according to one aspect of this invention, an arrangement is provided such that, a current having a higher level than a level of a write current is supplied for a desired period of time during rise and fall of the write current, and a current having a lower level than the level of the write current is supplied for a desired period of time during overshoot at the rise and fall of the write current.

In the magnetic record writing circuit according to another aspect of this invention, the current for driving a head is supplied by the action of a transistor group where the current source transistor is joined in parallel with at least one damping transistor and released from the head by the action of load transistors via a mirror transistor which comprises a reference current source and a mirror circuit.

Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.

FIG. 1 is a circuit diagram of the magnetic record writing circuit according to a first embodiment of the present invention;

FIG. 2 is a diagram showing the control waveform and other signals according to the first embodiment;

FIG. 3 is a diagram showing the control waveform and other signals according to a second embodiment;

FIG. 4 is a diagram of a conventional magnetic record writing circuit; and

FIG. 5 is a diagram of the waveform of conventional control and other signals.

FIG. 1 is a circuit diagram of the first embodiment of the present invention. The head 1 in this magnetic recording apparatus is identical to the same shown in FIG.

In FIG. 1, I 1 denotes reference current source for supplying a reference current for a write current Iw. The reference current source I 1 is connected at one terminal to the collector of an NPN transistor Q 1 and the base of another NPN transistor Q 2 . The base of the NPN transistor Q 1 is connected to the emitter of the NPN transistor Q 2 and the bases of further transistors Q 3 and Q 4 . The collector of the NPN transistor Q 2 as well as the other terminal of the current source I 1 are connected to a third power source V 3 . The emitter of the NPN transistor Q 1 and the emitters of the NPN transistors Q 3 and Q 4 are connected to a second power source V 2 via an NMOS transistor Q 5 , two NMOS transistors Q 6 and Q 8 , and two NMOS transistors Q 7 and Q 9 respectively. While the base of the NMOS transistor Q 5 is connected to a third power source V 3 , the bases of the NMOS transistors Q 6 , Q 7 , Q 8 , and Q 9 are connected to four terminals B, A, F, and E respectively.

The collector of the NPN transistor Q 3 is connected to the drain of a PMOS transistor Q 10 which is in turn connected at its source and back gate to the drain of a PMOS transistor Q 12 serving as the current source transistor and the drain of a PMOS transistor Q 14 serving as the damping transistor respectively.

The collector of the NPN transistor Q 4 is connected to the drain of the PMOS transistor Q 11 which is in turn connected at its source and back gate to the drain of a PMOS transistor Q 13 serving as the current source transistor and the drain of a PMOS transistor Q 15 serving as the damping transistor respectively.

The sources and back gates of the PMOS transistors Q 12 , Q 13 , Q 14 , and Q 15 are connected to the first power source V 1 . The gates of the PMOS transistors Q 10 and Q 11 are connected to a fourth power source V 4 . The PMOS transistors Q 10 and Q 11 act as the protective transistors for inhibiting the application of no breakdown voltage to between the source and the drain of each of the PMOS transistors Q 12 , Q 13 , Q 14 , and Q 15 . The use of the protective transistors is not mandatory so long as a voltage greater than the breakdown voltage is not applied between the source and the drain of each transistor.

The gates of the PMOS transistors Q 12 and Q 13 serving as the current source transistors are connected to two terminals D and C respectively. Also, the gates of the PMOS transistors Q 14 and Q 15 serving as the damping transistors are connected to two terminals H and G respectively.

FIG. 2 illustrates the waveform of voltage signals applied to the terminals A, B, C, D, E, F, G, and H, collector currents I 2 and I 3 at the corresponding NPN transistors Q 3 and Q 4 , drain currents I 4 and I 5 at the corresponding PMOS transistors Q 10 and Q 11 , and the current Iw at the head 1 .

As the NPN transistors Q 1 , Q 2 , Q 3 , and Q 4 are arranged in a current mirror circuit, the currents I 2 and I 3 running through the collectors of the corresponding NPN transistors Q 3 and Q 4 are proportional to the current I 1 as shown in FIG. 2 . The NOMS transistors Q 5 , Q 6 , Q 7 , Q 8 , and Q 9 are load transistors acting as the emitter resistors of the transistors Q 1 , Q 3 , and Q 4 in the current mirror circuit and can thus be switched on and off by their respective controls signals A, B, E, and F.

The voltages and currents at the terminals A to H will now be explained referring to FIG. 2 .

In the beginning, the terminals A, C, E, and F are fed with signals having low logical level, while the other terminals B, D, G, and H are fed with signals having high logical level. As the current Iw in the head 1 runs in the rightward direction, the current I 2 is allowed to flow constantly at a level of I 10 .

During the period T 1 , the terminals A, C, E, G, and H receive signals having high logical level while the terminals B, D, and F are fed with signals having low logical level. Hence, the current Iw in the head 1 runs in the leftward direction and is then increased by means of the capacitance C 1 as denoted by a 1 . At the time, as the two load transistors Q 7 and Q 9 are switched on, the currents I 3 and I 4 are at relatively a high level I 7 . Since the NPN transistor Q 4 is favorably reduced in the load resistance, the rise al of the current Iw becomes quicker than the rise a 7 shown in FIG. 5 .

This is followed by the period T 2 in which the terminals A, C, and H receives signals having high logical level while the other terminals B, D, E, F, and G are fed with signals having low logical level. As the current Iw in the head 1 remains running in the leftward direction, the NMOS transistor Q 9 is switched off and the PMOS transistor Q 15 is turned on. This shifts the current I 3 to a level I 8 and the current I 4 to a level I 11 . As a result, the current Iw is quickly declined to offset the overshoot at the rise (denoted by a 2 ).

During the period T 3 , the terminals A, C, G, and H are fed with signals having high logical level while the other terminals B, D, E, and F receive signals having low logical level. As the current Iw in the head 1 runs in the leftward direction at a constant level (a 3 ). At the time, the currents I 3 and I 4 are at the level I 8 .

The period T 4 then follows where the terminals B, D, F, G, and H receive signals having high logical level while the terminals A, C, and E are fed with signals having low logical level. Hence, the current Iw in the head 1 runs in the rightward direction and is then increased by means of the capacitance C 1 (a 4 ) similar to a 1 . At the time, as the two load transistors Q 6 and Q 8 are switched on, the currents I 2 and I 4 are at relatively high level I 9 . Since the NPN transistor Q 3 is favorably reduced in the load resistance, the fall a 4 of the current Iw becomes quicker than the rise a 9 shown in FIG. 5 .

B, D, and G receive signals having high logical level while the other terminals A, C, E, F, and H are fed with signals having low logical level. As the current Iw in the head 1 remains running in the rightward direction, the NMOS transistor Q 8 is switched off and the PMOS transistor Q 14 is turned on. This shifts the current I 2 to the level I 10 and the current I 4 to a level I 12 . As a result, the current Iw is quickly declined to offset the overshoot at the fall (denoted by a 5 ).

During the period T 6 , the terminals B, D, G, and H are fed with signals having high logical level while the other terminals A, C, E, and F receive signals having low logical level. As the current Iw in the head 1 runs in the rightward direction at a constant level (a 6 ). At the time, the currents I 3 and I 4 are at the level I 10 .

As described above, the current Iw in the head 1 has a waveform shown in FIG. 2 where the rise al can be controlled by the period T 1 and the current level I 7 . This will contribute to the faster rise of signals in the magnetic recording apparatus.

Also, the overshoot which is inevitable at the faster rise a 1 can successfully be offset by a 2 for having a stable waveform of the signal, hence allowing the signals in the magnetic recording apparatus to response faster. Equally, the overshoot at the fall a 4 can be offset by the overshoot recovery (a 5 ).

The waveform of the current Iw shown in FIG. 2 is reversed between the T 1 +T 7 period and the T 4 +T 8 period. This indicates that the current flows in opposite directions.

The current levels I 7 I 8 , I 9 , and I 10 can arbitrarily be determined to desired settings depending on the reference current I 1 and the transistor size of the load transistors Q 5 , Q 6 , Q 7 , Q 8 , and Q 9 . The current levels I 11 and I 12 can also be determined to desired settings depending on the transistor size of the PMOS transistors Q 10 , Q 11 , Q 14 , and Q 15 and the resistors R 1 and R 3 .

In addition, the periods T 1 , T 2 , T 4 , and T 5 may be determined to desired lengths using delay circuits or the like.

Power source by the PMOS transistors Q 15 , Q 11 , Q 10 , and Q 14 during the period T 2 , the PMOS transistors Q 15 , Q 11 , Q 10 , and Q 14 act as damping resistances for hastening the recovery a 2 to the level of a 3 . Also, during the period T 5 , the recovery a 5 is hastened to gain the level of a 6 .

As the current levels I 7 and I 9 are determined proportional to the reference current I 1 , the amplitude of the current Iw may be modified by changing the reference current I 1 but its waveform remains almost unchanged.

It is understood that the NPN transistors and the PMOS transistors in the circuit shown in FIG. 1 can be replaced by PNP transistors and NMOS transistors respectively without diminishing the above functions and effects.

The second embodiment of the present invention is shown in FIG. 3 where the waveform of voltages applied to the terminals A and B are different from those in the first embodiment. Resultant waveform of the current Iw in the second embodiment, however, is similar to that in the first embodiment.

In the second embodiment, the currents I 2 and I 3 are zero during the periods T 2 and T 5 . Accordingly, the consumption of power will be smaller than that of Embodiment 1.

Also, the periods T 1 , T 2 , T 4 , and T 5 can be determined by means of a DAC which permits more precise control over the waveform of the current Iw.

As explained above, in the magnetic record writing circuit of this invention, an arrangement is provided such that, a current having a higher level than a level of a write current is supplied for a desired period of time during rise and fall of the write current, and a current having a lower level than the level of the write current is supplied for a desired period of time during overshoot at the rise and fall of the write current. Therefore, sharp rise of the write current can be ensured.

Furthermore, when current having a higher level than a level of a write current is supplied, the level of the write current is not fixed but it is varied in proportion to the level of the write current. Therefore, there is no change the setting even if the level of the write current is changed.

Furthermore, MOS transistors are employed as the load transistors. Therefore, stable resistance can be achieved.

Furthermore, protective transistors are provided between the current source transistor and damping transistor and the mirror transistor. Therefore, it is prevented that a voltage greater than the breakdown voltage is applied to both the current source transistor and the damping transistor.

Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.