Combination multiplexer and tristate driver circuit

1. Field of the Invention

This invention relates to complimentary metal oxide semiconductor (CMOS) circuit designs, and more particularly, to multiplexer designs.

2. Description of the Related Art

In CMOS designs, traditional static CMOS multiplexer functions may typically be implemented using two or more stages of logic (e.g. a complex gate such as an and/or function). Each stage represents a gate delay to the input data. This means that the traditional static CMOS multiplexer may be slow. This may be especially true for multiple input multiplexers.

To reduce the gate delay and slow response of some static CMOS multiplexers, it is common to use pre-charge logic to implement wide fan-in bus drivers or other large multiplexer functions. Pre-charge logic is typically used to charge an output node to a binary one, and then if the output data is a binary zero, evaluating logic pulls the output node low. The pre-charging circuitry reduces the need for multiple logic stages used in static CMOS designs. Thus pre-charging may allow for a faster output response time. However, some CMOS multiplexer designs may require a large P-Channel load device per stage, which may have a large capacitance associated with it. Additionally, in cases where pre-charge logic may not be used such as, for example, when there is no clock available or the data is not synchronous to one of the clock edges, then a static CMOS multiplexer may be the only choice. Accordingly, it is desirable to have a faster multiple input static CMOS multiplexer design.

The problems outlined above may in large part be solved by a combination multiplexer and tristate driver circuit. A multiplexer circuit may be configured to receive at least a first data input and a second data input, which are selected by at least a first select signal and a second select signal, respectively. In one embodiment, a first circuit is configured to provide an output to an output node responsive to the data input that is selected by the corresponding select signal being active. The multiplexer circuit may further use a tristate circuit, which is also coupled to receive the first select signal and the second select signal. If neither the first select signal nor the second select signal are active, then the tristate circuit is configured to prevent the first circuit from providing an output to the output node. Thus, the multiplexer circuit may be used to build larger multiplexers by instantiating the multiplexer circuit multiple times.

Broadly speaking, in one embodiment, a multiplexer circuit is contemplated comprising a first circuit coupled to receive at least a first data input and a second data input. The first circuit is also coupled to receive at least a first select signal and a second select signal corresponding to the first data input and the second data input, respectively. The first circuit is coupled to an output node and is configured to provide an output on the output node responsive to a corresponding one of the first select signal or the second select signal being active. The multiplexer circuit may also include a tristate circuit coupled to receive the first select signal and the second select signal. The tristate circuit is also coupled to the first circuit. The tristate circuit is configured to prevent the first circuit from providing an output on the output node responsive to the first select signal and the second select signal being inactive.

In an alternative embodiment, a multiplexer circuit comprising a first multiplexer circuit is coupled to a first data input and a second data input. The first multiplexer circuit is also coupled to a first select signal and a second select signal corresponding to the first data input and the second data input, respectively. The first multiplexer circuit is configured to provide an output on an output node responsive to a corresponding one of the first select signal or the second select signal being active and to provide no output on the output node responsive to the first select signal and the second select signal being inactive. The multiplexer circuit may also include a second multiplexer circuit coupled to a third data input and a fourth data input. The second multiplexer circuit is also coupled to a third select signal and a fourth select signal corresponding to the third data input and the fourth data input, respectively. The second multiplexer circuit is configured to provide an output on the output node responsive to a corresponding one of the third select signal or the fourth select signal being active and to provide no output on the output node responsive to the first select signal and the second select signal being inactive.

In addition, a method of operating a multiplexer circuit is contemplated. In one embodiment, at least a first data input and a second data input are received by the multiplexer circuit. Additionally, at least a first select signal corresponding to the first data input and a second select signal corresponding to the second data input are also received by the multiplexer circuit. The multiplexer circuit provides an output on an output node responsive to a corresponding one of the first select signal or the second select signal being active. The multiplexer provides no output on the output node responsive to the first select signal and the second select signal being inactive.

Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which:

FIG. 1 is a circuit diagram of one embodiment of a two input multiplexer.

FIG. 2 is a circuit diagram of one embodiment of a four input multiplexer circuit.

FIG. 3 is a circuit diagram of an alternative embodiment of a four input multiplexer circuit.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims.

Turning now to FIG. 1 , a circuit diagram of one embodiment of a two input multiplexer is shown. The multiplexer circuit illustrated in FIG. 1 includes ten transistors, four of which are P-channel CMOS transistors and six are N-channel CMOS transistors. A P-channel transistor T 1 is connected in series with another P-channel transistor T 2 . One end of the series connection is connected to a positive power supply voltage VDD. The other end of the series connection is connected to the gate terminal of a P-channel transistor T 10 . The gate terminal of transistor T 1 is connected to select signal s 0 and the gate of transistor T 2 is connected to select signal s 1 .

The select signals s 0 and s 1 are also connected to the gates of an N-channel transistor T 4 and an N-channel transistor T 3 , respectively. Transistors T 3 and T 4 are connected in parallel such that their output terminals are connected together. The input terminal of transistor T 4 is connected to a data input signal d 0 and the input terminal of transistor T 3 is connected to a data input signal d 1 .

An N-channel transistor T 5 is connected in series with an N-channel transistor T 6 . An N-channel transistor T 7 is connected in series with an N-channel transistor T 8 . The two series pairs of transistors are connected in parallel such that the output of transistor T 5 and the output of transistor T 7 are connected together. This connection is an output node 10 . The other ends of the series connections are both connected to a circuit ground GND. The gate terminal of transistor T 5 is connected to select signal s 0 and the gate terminal of transistor T 7 is connected to select signal s 1 . The gate terminal of transistor T 6 is connected to data input signal d 0 and the gate terminal of transistor T 8 is connected to data input signal d 1 .

One terminal of transistor T 10 is connected to VDD, while the other terminal is connected to output node 10 . Output node 10 is also connected to the gate terminal of a P-channel transistor T 9 . One terminal of transistor T 9 is connected to VDD while the other terminal is connected to the gate of transistor T 10 . Output node 10 may also be connected to a data bus d_bus 50 .

The multiplexer circuit may be thought of as having two main sub-circuits: a charge and discharge circuit 15 and a tristate circuit 5 . Charge and discharge circuit 15 is configured to charge or discharge output node 10 (thus providing a binary one or binary zero output, respectively) responsive to an active select signal and the data on the corresponding data signal. More particularly, charge and discharge circuit 15 may charge the output node 10 (providing a binary one) responsive to a selected data input being binary zero, and may discharge the output node 10 (providing a binary zero) responsive to a selected data input being a binary one. In other words, charge and discharge circuit 15 may provide an inverting multiplexing function. Other embodiments may provide a non-inverting multiplexing function.

In the illustrated embodiment, charge and discharge circuit 15 may include two subcircuits: A charging circuit 25 that includes transistors T 3 , T 4 , T 9 and T 10 and a discharging circuit 35 that includes transistors T 5 , T 6 , T 7 and T 8 . Charging circuit 25 charges output node 10 to VDD (a binary one) responsive to data present on the data input if the corresponding select signal is active. More particularly, charging circuit 25 charges output node 10 responsive to a binary zero on the selected data input. Discharging circuit 35 discharges output node 10 to GND (a binary zero) responsive to data present on the data input if the corresponding select signal is active. More particularly, discharging circuit 35 discharges output node 10 responsive to a binary one on the selected data input.

Tristate circuit 5 includes transistor T 1 and transistor T 2 . Tristate circuit 5 prevents charge and discharge circuit 15 from providing on output on output node 10 if neither of the select signals are active. More particularly in the illustrated embodiment, tristate circuit 5 causes VDD to be applied to the gate of transistor T 10 when neither of the select signals are active. Thus, transistor T 10 is off. When neither select signal is active, the series transistor connections T 5 /T 6 and T 7 /T 8 are off as well, preventing discharge of the output node 10 . Accordingly, output node 10 may be floating when neither of the select signals are active.

The embodiment in FIG. 1 is shown using CMOS transistors. It is contemplated that other embodiments may use any suitable set of transistors that may be manufactured in technologies other than CMOS.

As noted above, this embodiment illustrates a two input multiplexer. This particular embodiment has two select signals s 0 and s 1 that control which data input is selected as the output. One of the data input signals is selected by activating the corresponding select line. In this embodiment an active signal refers to a binary one, and conversely, an inactive signal refers to a binary zero. It is noted that in other embodiments, an active signal may be a binary zero, while an inactive signal may be a binary one. It is also noted, that while this embodiment illustrates a two input multiplexer, it is contemplated that other embodiments may be N input multiplexers. For example, a four input multiplexer is illustrated below.

The operation of the multiplexer circuit shown in FIG. 1 will next be described. First, operation will be described for data input signals d 0 and d 1 being a binary zero (represented by a GND voltage level). To select data input d 0 , a binary one (represented by a VDD voltage level) is input on select signal s 0 and a binary zero is input on select signal s 1 . In this example, the binary zero on s 0 causes transistor T 1 not to conduct (referred to as being “off” or in an “off state”), while transistor T 2 is conducting (referred to as being “on” or in an “on state”). The binary one on select signal s 0 is also applied to the gates of transistor T 4 and transistor T 5 , causing both to turn on. The binary zero on data input d 0 is applied to the gate of transistor T 6 , which is therefore off. Accordingly, the series connection of transistors T 5 and T 6 does not discharge output node 10 . Since transistor T 4 is on, the binary zero on data input d 0 is passed through transistor T 4 to the gate of transistor T 10 , causing it to turn on. Transistor T 10 charges output node 10 (and therefore d_bus 50 ) to VDD. Thus the binary zero input on data input d 0 is inverted and a binary one is present at output node 10 . In other words, in this embodiment, the multiplexer is an inverting multiplexer. Other embodiments may be non-inverting, (e.g. by adding an inverting stage at output node 10 ). The binary one on output node 10 is also applied to the gate of transistor T 9 , which is therefore off.

With the select signals s 0 and s 1 the same as above, operation will now be described for data input d 0 being a binary one. The signal path that the data follows is the same as above. However, the result is different. A binary one passes through transistor T 4 to the gate of transistor T 10 , which causes transistor T 10 to turn off. The binary one is also applied to the gate of transistor T 6 , turning it on. Since transistor T 5 is on due to select signal s 0 , the series connection of transistors T 5 and T 6 discharges output node 10 to GND. Thus the binary one present on data input d 0 is inverted to a binary zero at output node 10 . As output node 10 approaches ground, or a binary zero, transistor T 9 turns on and causes VDD to be applied to the gate of transistor T 10 , thereby assuring that transistor T 10 is in the off state.

Operation of the multiplexer circuit when select signal s 0 is deactivated and select signal s 1 is active is similar to the above description, with transistor T 7 corresponding to transistor T 5 , transistor T 8 corresponding to transistor T 6 , and transistor T 3 corresponding to transistor T 4 .

Next, the case when neither select signal s 0 nor s 1 are active is described. Both transistor T 1 and transistor T 2 are on, charging the gate of transistor T 10 to VDD. The binary zeros present on both select signal s 0 and s 1 are applied to the gates of transistors T 3 , T 4 , T 5 and T 7 , turning them off. Turning off transistors T 3 and T 4 prevents the data present on data input d 0 and d 1 from passing to the gate of transistor T 10 . Turning off transistors T 5 and T 7 prevents discharging of output node 10 to GND. In this way, output node 10 is allowed to “float”, which is also referred to as being in tristate. Since the impedance seen by any load that may be attached to d_bus 50 looking into output node 10 is high, it is also referred to as a high impedance state. This tristate feature will be described in more detail below.

Referring to FIG. 2 , a circuit diagram of one embodiment of a four input multiplexer circuit is illustrated. The four input multiplexer shown in FIG. 2 includes a first two input multiplexer circuit, multiplexer 1 and a second two input multiplexer, multiplexer 2 . The output nodes of multiplexer 1 and multiplexer 2 are connected in parallel such that an output node 10 of multiplexer 1 and an output node 20 of multiplexer 2 are both connected to d_bus 50 . The four data input signals are d 0 , d 1 , d 2 , d 3 and the four corresponding select signals are s 0 , s 1 , s 2 , s 3 , respectively.

Both multiplexer 1 and multiplexer 2 are instantiations of the multiplexer circuit of FIG. 1 . The tristate circuit described above in the description of FIG. 1 enables multiple two input multiplexers to be connected to a common output node by causing each multiplexer output node to be placed in a high impedance state when neither of the respective multiplexer select lines is active. For example, in FIG. 2 , if select signal s 2 is active, then s 0 , s 1 and s 3 are inactive. This places output node 10 of multiplexer 1 in a high impedance state allowing multiplexer 2 to drive data onto d_bus 50 without bus contention. The high impedance state of the inactive multiplexer allows the basic two input multiplexer of FIG. 1 to be instantiated N times to produce a 2 N input multiplexer. The ability to instantiate the basic multiplexer may also provide circuit layout efficiency.

Turning now to FIG. 3 , a circuit diagram of an alternative embodiment of a four input multiplexer circuit is shown. As will be described in more detail below, the four input multiplexer circuit of FIG. 3 is similar in operation to that of the two input multiplexer circuit described in FIG. 1 with the addition of two select signals s 2 and s 3 , two data input signals d 2 and d 3 and some additional transistors to accommodate the additional input signals.

Referring back to FIG. 1 , P-channel transistors T 1 , T 2 , are connected in series and turn off P-channel transistor T 10 in the event that neither input signal s 0 nor s 1 is active. In FIG. 3 , P-channel transistors T 3 and T 4 are added in series with transistors T 1 and T 2 . The four series transistors turn off P-channel transistor T 18 when none of the four select signals s 0 , s 1 , s 2 or s 3 is active. Transistor T 17 performs the same function as transistor T 9 in FIG. 1 . N-channel Transistors T 5 and T 6 of FIG. 3 perform the same operation as transistors N-channel T 3 and T 4 in FIG. 1 . N-channel transistors T 7 , T 8 , T 9 and T 10 of FIG. 3 perform the same operation as N-channel transistors T 5 -T 8 of FIG. 1 .

N-channel transistors T 11 -T 14 of FIG. 3 perform a similar operation to that of transistors T 7 -T 9 , but they are responsive to data input signals d 2 and d 3 and select signals s 2 and s 3 . Likewise, N-channel transistors T 15 and T 16 perform a similar operation to that of transistors T 5 and T 6 , but they are responsive to data input signals d 2 and d 3 and select signals s 2 and s 3 .

As described above in the description of FIG. 2 , the four input multiplexer of FIG. 3 may also be instantiated N times to construct a 4 N input multiplexer circuit by connecting the output nodes of each of the four input multiplexers together.

Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.