Feed forward error correction in video decoder

This application claims priority under 35 USC § 119(e)(1) of provisional application Ser. No. 60/205,548, filed May 22, 2000.

This invention relates to video decoders and more particularly to error correction in video decoders.

The composite video signal sent from a video source includes color video information (which includes the chrominance signal conveyed by means of a subcarrier) as well as timing information for the accurate reproduction of the active video (e.g. reproduction of the picture information including its correct colors). This signal is essentially a video stream that combines, as a one signal, all of the elements required for displaying an image. The timing information is conveyed through the transmission of synchronization signals. A synchronization signal is commonly referred to as sync. In conjunction with a receiver which displays pixel information according to the video picture transmitted, an electric beam scans the receiver's display according to the horizontal sync signal followed by a horizontal blanking interval during which time the beam is shut off so that it can spot retrace horizontally across the display without being observed. Once the display has been scanned from top to bottom, the vertical sync signal determines when the beam is returned to the top of the display during the vertical blanking interval during which time the beam is shut off so that it can spot retrace vertically across the display without being observed. A composite video signal generally includes active video, horizontal sync, horizontal blanking, vertical sync, vertical blanking, and color burst. The color burst is that portion of the video waveform that sits between the breezeway (the portion of the video waveform between the rising edge of the horizontal sync and the start of the color burst) and the start of the active video. The color burst allows the color decoder to decode the color information contained in a line of active video. In a receiver or video decoder, the color phase locked-loop maintains lock of the local color oscillator with the color burst of the composite video input signal.

Conventional horizontal phase-locked loops for video decoders serve the purpose of locking the sampling clock, for clocking digital pixel information into the phase-locked loop, to the falling edge of the incoming horizontal sync of composite video information. This lock is required to generate a stable picture in the horizontal direction and position signals which identify the sync tip, back porch, and the color burst of the composite video. The analog video information enters an analog-to-digital converter which outputs digital pixel information. A pixel counter counts video information corresponding to pixels in what can be considered a horizontal scan line across a display monitor screen such as a cathode ray tube. The pixel counter starts with a count of zero and counts to a terminal count and then falls back to zero. The phase-locked loop employs two modes of lock; a coarse lock and a fine lock. In the coarse lock mode the incoming horizontal sync pulse which is usually present during the blanking interval of each line associated with the video signal (for the purpose of being able to synchronize the scanning of the monitor with the scanning of the original image), is detected by an analog circuit. Based on the decode of the pixel counter, a coarse gate filter window (meaning a relatively wide time window in comparison with the narrow time window associated with the fine window discussed below) is enabled around the time the horizontal sync pulse is expected. If the sync does not occur within the gate window for a time corresponding to several consecutive video lines, then either the pixel counter is reset or a correction is made to the clock frequency of the video decoder system in order to move the window to the sync pulse. When the sync pulse falls within the fine lock window, then the fine lock mode is enabled. A fine gate filter window is employed by the fine lock mode which enables a phase detector which calculates a phase error based upon the position of the edge of the sync pulse within a narrow window known as the fine lock window. This phase error is then filtered by a loop filter whose output is fed to a discrete time oscillator (DTO) which adjusts the clock frequency to move the sync pulse so that its edge is centered in the fine window, thereby minimizing the phase error. Prior art horizontal phase-locked loop schemes are generally implemented according to analog hardware, digital hardware or a combination of analog and digital hardware. A major drawback of this type of implementation lies in the inconvenience of changing parameters to adapt to a particular video scheme, e.g. NTSC, PAL, NPAL, MPAL, etc.

A digital version of the horizontal phase locked loop is described in application Ser. No. 09/126,630 filed Jul. 30, 1998 of Karl Renner et al. entitled “Horizontal Phased-Locked Loop for Video Decoder” and now abandoned. This application is incorporated herein by reference.

A digital version of the color oscillator in video decoder is called a color discrete time oscillator (DTO). The color phase lock loop is normally controlled by generating the phase error between the color burst input and the locally generated color frequency. The phase error is computed during the color burst interval by accumulating the product of the color burst input pixels and the cosine of the local color oscillator cos w sc t. The phase error is then filtered and added to a nominal color DTO increment value and then written to the color DTO. This occurs once per scan line. The phase error may also be accumulated in a register such that any frequency offset may be detected and added to the color DTO increment. This technique works fine if the pixel clock frequency is stable. Wide deviations can occur in nonstandard video such as television games. The video cassette recorder (VCR) is another source of nonstandard video. In the case of the VCR, head switching transience can cause the horizontal sync frequency to jump by as much as 16 microseconds during the vertical sync interval. However, should the pixel clock frequency vary (as it can with VCR inputs), problems can arise in efforts to accurately reproduce color content on a display. A microprocessor based system is needed in order to provide a highly adaptable and improved horizontal phase-locked loop as well as an improved color phase-locked loop.

The frequency and phase of the color DTO is controlled by an increment value written to it by a microprocessor. The color DTO is clocked by the pixel (picture element) sampling clock. The color phase lock loop (PLL) must be able to lock to the color burst frequencies. Since the color burst frequencies can deviate from the nominal frequency, the horizontal phase lock loop (PLL) must make coarse corrections in its timing in order to maintain lock to this input. Since the color DTO is clocked by the pixel clock, corresponding coarse correction must be made to it such that the stability of the local color oscillator is maintained and color lock is not lost.

In the TVP5020 video decoder of Texas Instruments Inc., the pixel clock frequency variations due to horizontal sync jitter are compensated by a feed forward term from the horizontal phase-lock loop to the color phase-lock loop. This term is a function of the inverse of the increment delta required by the horizontal PLL to maintain lock to the horizontal sync input as shown below.

inc h =nom — inc sc /(1+Δ h /nom _inc h ).

The inverse requires a division operation which results in a lot of computational overhead in either software or hardware to implement.

In accordance with one embodiment of the present invention variations in pixel clock frequency are compensated by the addition of the feed forward error to the color PLL increment delta.

In accordance with another embodiment of the present invention the feed forward error is a scaled version of the horizontal DTO increment delta which does not require division as implemented in the previous design. This results in greater accuracy.

In accordance with another embodiment of the present invention the scaling is implemented using adds and shifts.

FIG. 1 is a block diagram of the horizontal PLL and color PLL system according to a preferred embodiment of the present invention;

FIG. 2 illustrates an implementation of feed forward error using adds and shifts, and

FIG. 3 is a block diagram of feed forward in color PLL processing.

A description of the horizontal phase locked loop for the TVP 5020 is found in the above-mentioned application Ser. No. 09/126,630 The present invention concerns a video decoder including a color phase lock loop which maintains lock of the local color oscillator with the color burst of the composite video input signal. The color phase-locked loop for the TVP 5020 is described in U.S. Pat. No. 6,330,034 entitled Color Phased-Locked Loop for Video Decoder”. This patent is incorporated herein by reference. The TVP5020 utilizes a 24 bit accumulator and the resulting relationship between increment and pixel clock frequency f pix is shown below where the crystal oscillator frequency f crystal is 24.576 MHz for the 601 sampling rate and 26.8.MHz for the square pixel sampling rate. The horizontal DTO increment inc is a direct function of f pix which results in

inc h =2 23 *f pix /f crystal .

A color DTO increment inc sc which is a function of the inverse of the increment delta(Δh) required by the horizontal PLL to maintain lock to the horizontal sync input is shown below

inc sc =nom — inc sc /(1+Δ h /nom — inc h ).

This inverse requires a division operation which results in a lot of computational overhead to implement in either hardware or software to implement. This technique is described in the above-mentioned U.S. Pat. No. 6,330,034. This application is incorporated herein by reference. The horizontal phased-locked loop for this feed forward is described in the the above-mentioned application Ser. No. 09/126,630.

Referring to FIG. 1 there is illustrated horizontal phase locked loop (PLL) 11 and color PLL 13 which are implemented in a combination of hardware and software according to a preferred embodiment of the present invention. The horizontal phased-locked loop is described in U.S. Pat. No. 6.329,850 entitled “Precision Frequency and Phase Synthesis”. This patent is incorporated herein by reference. This horizontal DTO is a difference architecture that minimizes jitter. The horizontal discrete time oscillator (DTO) has a different increment/frequency from that in the TVP 5020 which is shown below where f ring is the ring oscillator frequency which is based on a crystal frequency=to 10*4*f sc =14.31818 MHz. The color subcarrier frequency f sc is 3.58 MHZ for NTSC.

inc= 2 27 *(31/8* f ring /f pix +1).

There is an inverse relationship between the inc and f pix which results in a great simplification of the feed forward error correction obtained from the horizontal PLL fed to the color PLL. The horizontal discrete time oscillator(DTO) 15 is clocked by a constant frequency f ring from a ring oscillator 14 . The ring oscillator frequency f ring is referenced to a crystal oscillator frequency f ring by the relation f ring =m*f crystal . Typical values are m=10 and f crystal =4*f sc where f sc is the local color subcarrier oscillator frequency. The horizontal DTO 15 output frequency is divided down by 8 by divider 17 to produce the pixel clock frequency f pix . A pixel counter 19 and decoder 21 are responsive to the f pix to produce a fine lock window signal which is then compared to the horizontal sync at phase detector 23 and any phase error is sent to the microprocessor 22 . The decoder includes the coarse phase detector and fine phase detector described in the referenced horizontal phased-locked loops. The microprocessor 22 reads the horizontal phase error, filters it and writes an increment inc h value to the horizontal DTO 15 to maintain lock to the horizontal sync input. The pixel clock frequency f pix , in turn, drives the color DTO 27 which generates the local oscillator frequency f sc via the cosine ROM 29 . The local color oscillator frequency f sc and the received color burst are applied to the color phase detector 31 and the phase error is applied to the microprocessor 22 . The microprocessor 22 reads the phase error between the color burst input and f sc , filters it, and writes an increment inc sc value to the color DTO 27 to maintain lock to the color burst input. The following two equations relate the horizontal DTO 15 and color DTO 27 frequencies to their inputs.

inc h =2 27 *(31/8 *f ring /f pix +1)

inc sc =2 24 *f sc /f pix

These two equations are combined to eliminate f pix and generate a result for inc sc as a function of inc h .

inc sc =8/31*2 24 *(2 −27 *inc h −1)* f sc /f ring

As the horizontal PLL 11 adjusts inc h varies about its nominal nom inc h by Δ h .

inc h =nom — inc h +Δ h

Substitution for inc h results in the following.

inc sc =nom — inc sc +1/31 *f sc /f ring *Δ h

The feed forward error term from the horizontal PLL is 1/31*f sc /f ring *Δ h . This represents the required adjustment to the color DTO 27 in order to maintain a constant f sc . This relation requires only the addition of a scaled version of Δ h . For f ring =10*4*f sc the feed forward scale factor can be approximated by 53/2 16 which can be rewritten in binary as 11010 2 right shifted 16 bits. FIG. 2 illustrates an implementation. Bits 1 , 2 , 4 and 5 are summed at summer 50 and right shifted 16 bits at shifter 51 .

FIG. 3 illustrates the application of the feed forward error in the color phase loop processing performed within the microprocessor 22 software where it is simply added to the color PLL increment delta of FIG. 1 . The burst phase error, corresponding to a particular line of video, as determined by microprocessor 22 after processing some function of the filter output is right shifted n bits by microprocessor 22 . The n bit shift is illustrated by block 60 . This corresponds to multiplication by a proportional shift constant k p . This result is added (represented by block 62 ) to a previous video line result (represented by block 64 and delay) corresponding to a previous burst error for the previous line. The resulting two line sum is negated (block 66 ). The negative two line sum is accumulated with summer 68 , using a line delayed feedback loop that limits the summed results between positive and negative limits by virtue of block limit 69 and delay line block 70 . The accumulated and limited sum is right shifted in bits by functional right shift block 72 . This corresponds to multiplication by an integral constant k i . The resulting product is added at adder 80 to the negative two line sum and to the scaled feed forward error (feed_forward_error) term from the horizontal PLL (for example 1/31*f sc /f ring *Δh) as discussed above in connection with FIG. 2 for example. The feed forward error is a scaled version of the horizontal DTO increment that does not require division. The scaling can be implemented by adds and shifts. The sum of the functional adder 80 is added to the nominal color DTO increment (nom_color_DTO_inc) by functional adder 82 . The variation in the pixel clock frequency are compensated by the addition of the feed forward error to the color PLL increment delta.

Although the present invention and its advantages have been described in detail, it should be understood that various changes substitutions and alterations can be made without departing from the spirit and scope of the invention as defined by the appended claims.